Ex Parte Klecka et alDownload PDFBoard of Patent Appeals and InterferencesApr 5, 201111346736 (B.P.A.I. Apr. 5, 2011) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ Ex parte JAMES S. KLECKA, WILLIAM F. BRUCKERT, MIHAI DAMIAN, PETER A. REYNOLDS, and DALE E. SOUTHGATE ____________ Appeal 2009-008764 Application 11/346,7361 Technology Center 2100 ____________ Before JOSEPH L. DIXON, JEAN R. HOMERE, and THU A. DANG, Administrative Patent Judges. HOMERE, Administrative Patent Judge. DECISION ON APPEAL 1 Filed on February 3, 2006. This application claims priority from provisional application 60/675,810, filed April 28, 2005. The real party in interest is Hewlett-Packard Development Co., L.P. (App. Br. 3.) Appeal 2009-008764 Application 11/346,736 2 I. STATEMENT OF THE CASE Appellants appeal under 35 U.S.C. § 134(a) (2002) from the Examiner’s final rejection of claims 1 through 5, 7 through 9, 12 through 15, and 17 through 20. (App. Br. 5.) Claims 11 and 16 have been allowed. (Id.; see also Fin. Rej. 8.) Claims 6, 10, and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. (Id.) We have jurisdiction under 35 U.S.C. § 6(b) (2008). We affirm. Appellants’ Invention Appellants invented a method and apparatus for presenting an interrupt request to two processors in lock step or loose-lock step, such that the two processors act as a single processor. (Tit.; see also Spec. 4, ¶ [0019].) Illustrative Claim Independent claims 1 and 17 further illustrate the invention as follows: 1. A computer system comprising: a first processor having a processor bus, the first processor configured to execute a program; a second processor having a processor bus, the second processor configured to execute a duplicate copy of the program in lock step with the first processor; and a logic device coupled to the processor bus of the first processor, and the processor bus of the second processor, the Appeal 2009-008764 Application 11/346,736 3 logic device configured to receive read operations from the first and second processors over the respective processor buses; wherein the logic device is configured to present an interrupt request to the processors when the processors are at substantially the same computational point in the program. 17. A computer system comprising: a first means for processing software instructions, the first means for processing configured to execute a program; a second means for processing software instructions, the second means for processing configured to execute a duplicate copy of the program in lock step with the first means for processing; a means for presenting an interrupt request to the first and second means for processing when the means for processing are substantially at the same computational point in the program. Prior Art Relied Upon The Examiner relies on the following prior art as evidence of unpatentability: Cutts US 4,965,717 Oct. 23, 1990 Rejections on Appeal The Examiner rejects claims 1 through 5, 7 through 9, 12 through 15, and 17 through 20 under 35 U.S.C. § 102(b) as being anticipated by Cutts. Appellants’ Contentions 1. Appellants contend that the Examiner improperly relies on devices spanning different Central Processing Unit (hereinafter “CPU”) boards to teach the “logic device,” as recited in independent claim 1. (App. Appeal 2009-008764 Application 11/346,736 4 Br. 13; Reply Br. 1-2.) In particular, since the present Specification indicates that the claimed “logic device” resides on a single board with the processors to which it is attached, Appellants argue that Cutts’ disclosure of a logic device within each CPU cannot teach “a logic device coupled to the processor bus of the first processor, and the processor bus of the second processor,” as claimed. (App. Br. 14; Reply Br. 2.) Appellants also argue that Cutts’ logic device within each CPU does not have the capability to receive “read operations from the first and second processors over the respective processor buses,” as claimed. (App. Br. 14.) 2. Appellants contend that the present Specification indicates that the logic device co-located on a single CPU board with two processors performs the claimed “means for presenting an interrupt,” as recited in independent claim 17. (Id. at 15-16.) In particular, Appellants argue that Cutts’ logic device only delivers an interrupt to the processor chip co-located on the same CPU board and, therefore, is not configured “to present an interrupt request to the processors when the processors are at substantially the same computational point in the program,” as claimed. (Id. at 16.) Further, Appellants disagree with the Examiner’s position that only functionality and not structure must be found in Cutts’ disclosure to teach the means-plus-function limitations set forth in independent claim 17. (Reply Br. 2-3.) Appellants allege that since the present Specification does not indicate that the structure for performing the claimed “means for presenting an interrupt” spans a plurality of CPU boards, Cutts cannot teach the disputed limitation. (Id.) Appeal 2009-008764 Application 11/346,736 5 Examiner’s Findings and Conclusions 1. The Examiner finds that the claimed “logic device” coupled to processor buses is only limited in terms of functionality and not structure. (Ans. 8-9.) Therefore, the Examiner finds that Cutts’ disclosure of an interrupt synchronization and voting circuit (hereinafter “ISV circuit”) located within a CPU teaches the “logic device,” as recited in independent claim 1. (Id. at 9.) Moreover, the Examiner finds that independent claim 1 does not include language that limits the claimed “logic device” to a single CPU board. (Id. at 10.) 2. Upon reviewing Appellants’ Specification for context, the Examiner broadly, but reasonably construes the claimed “means for presenting an interrupt request,” as a logic device that presents the interrupt request. (Id. at 11-12.) The Examiner finds Cutts’ ISV circuit performs the same function of presenting interrupt requests as the logic device. (Id. at 12.) Further, the Examiner finds that claimed “means for presenting an interrupt request” should not be limited by the environment on which the logic device is mounted because it is the logic device and not a single CPU board that performs the recited function. (Id. at 12.) II. ISSUES 1. Have Appellants shown that the Examiner erred in finding that Cutts anticipates independent claim 1? In particular, the issue turns on whether Cutts describes “a logic device coupled to the processor bus of the first processor, and the processor bus of the second processor, the logic device configured to receive read operations from the first and second processors over the respective processor buses.” Appeal 2009-008764 Application 11/346,736 6 2. Have Appellants shown that the Examiner erred in finding that Cutts anticipates independent claim 17? In particular, the issue turns on whether Cutts teaches the following claim limitation: “a means for presenting an interrupt request…” or its equivalents. III. FINDINGS OF FACT The following Findings of Fact (hereinafter “FF”) are shown by a preponderance of the evidence. Cutts FF 1. Cutts’ figure 1 depicts a computer system that has three identical processors, referred to as CPU-A (11), CPU-B (12), and CPU-C (13), which operate as one processor. (Col. 3, l. 65-col. 4, l. 1.) FF 2. Cutts’ figure 2 depicts one of the three processors in more detail (e.g, CPU-A (11)). (Col. 5, ll. 66-68.) Cutts also discloses that all three processors have the same construction. (Id.) In particular, Cutts discloses that the microprocessor chip (40) in each processor is coupled to a local bus having a data bus (41), an address bus (42), and a control bus (43). (Col. 6, ll. 38-40.) Further, Cutts discloses that the local bus (41, 42, & 43) is coupled to an internal bus structure via a write buffer (50) and read buffer (51). (Id. at ll. 48-50.) FF 3. Cutts’ figure 2 also depicts applying interrupts to the microprocessor chip (40) by one of the pins of the control bus (43 or 55) from an interrupt circuit (65) located in CPU-A (11). (Col. 8, ll. 12-14.) In particular, Cutts discloses that the interrupt circuit (65) in CPU-A (11) receives interrupt pending inputs (66) from CPU-B (12) and CPU-C (13), and sends an interrupt pending signal to the CPU-B (12) and CPU-C(13) via Appeal 2009-008764 Application 11/346,736 7 line (67). (Id. at ll. 18-21.) Cutts discloses that line (67) is part of the bus (18) connecting CPU-A (11), CPU-B (12), and CPU-C (13). (Id. at ll. 21- 22.) IV. ANALYSIS Claim 1 Independent claim 1 recites, in relevant part, “a logic device coupled to the processor bus of the first processor, and the processor bus of the second processor, the logic device configured to receive read operations from the first and second processors over the respective processor buses.” As detailed in the Findings of Fact section above, Cutts discloses three processors that operate as one processor. (FF 1.) In particular, Cutts discloses that each processor contains a microprocessor chip that is coupled to a control bus. (FF 2.) Further, Cutts discloses that the control bus is coupled to a read buffer and a write buffer via an internal bus structure. (Id.) Additionally, Cutts discloses that an interrupt circuit located in each processor applies interrupts to the microprocessor chip via the control bus. (FF 3.) Cutts discloses that the interrupt circuit is capable of both receiving interrupts pending inputs from the other two processors, and sending an interrupt pending signals to the other two processors. (Id.) We find that Cutts’ disclosure describes a first interrupt circuit coupled to the control bus of a first processor. Moreover, since the first interrupt circuit is capable of receiving and sending interrupts to a second processor, we find that Cutts’ disclosure also discloses that the first interrupt circuit is indirectly connected to the control bus of the second processor. Thus, we find that Cutts discloses “a logic device coupled to the processor Appeal 2009-008764 Application 11/346,736 8 bus of the first processor, and the processor bus of the second processor,” as recited in independent claim 1. Further, since Cutts discloses that the control bus of the first processor is coupled to a read buffer, we find that the first interrupt circuit is capable of receiving read operations from the first processor. Moreover, since the first interrupt circuit is indirectly connected to the control bus of the second processor, we find that the first interrupt circuit is also capable of receiving read operations from the second processor. Thus, we find that Cutts discloses that “the logic device [is] configured to receive read operations from the first and second processors over the respective processor buses,” as recited in independent claim 1. Alternatively, we note that the disputed claim limitation only requires that “the logic device [is] configured to receive read operations from the first and second processors over the respective processor buses.” (Emphasis added.) We find that this recitation merely requires that the logic device be capable of receiving read operations from the first and second processors over the respective processor buses. Such recitation does not require, however, that the logic device actually perform the recited function of receiving read operations from the first and second processors over the respective processor buses. This recitation is a statement of intended use, which is fully met by a prior art structure that is capable of performing the recited function. A statement of intended use in an apparatus claim cannot distinguish over a prior art apparatus that discloses all the recited limitations and is capable of performing the recited function. See In re Schreiber, 128 F.3d 1473, 1477 (Fed. Cir. 1997). We note that “[a]n intended use or purpose usually will not limit the scope of the claim because such statements Appeal 2009-008764 Application 11/346,736 9 usually do no more than define a context in which the invention operates.” Boehringer Ingelheim Vetmedica, Inc. v. Schering-Plough Corp., 320 F.3d 1339, 1345 (Fed. Cir. 2003). Although “[s]uch statements often . . . appear in the claim's preamble,” In re Stencel, 828 F.2d 751, 754 (Fed. Cir. 1987), a statement of intended use or purpose can appear elsewhere in a claim. Id. We are therefore satisfied that the Cutts teaches an equivalent structure that is capable of receiving read operations from the first and second processors over the respective processor buses. (FFs 2 & 3.) It follows that Appellants have not shown that the Examiner erred in finding that Cutts anticipates independent claim 1. Claims 2 through 5, 7 through 9, and 12 through 15 Appellants do not provide separate arguments for patentability with respect to independent claims 7 and 12, and dependent claims 2 through 5, 8, 9, and 13 through 15. Therefore, we group the claims together and select independent claim 1 as representative of the cited claims. Consequently, Appellants have not shown error in the Examiner’s rejection of independent claims 7 and 12, and dependent claims 2 through 5, 8, 9, and 13 through 15, for the reasons set forth in our discussion of independent claim 1. See 37 C.F.R. § 41.37(c)(1)(vii). Claim 17 Independent claim 17 recites, in relevant part, “a means for presenting an interrupt request . . . ”. We begin our analysis by noting that both Appellants and Examiner agree that the “means for” language found in independent claim 17 invokes 35 U.S.C. § 112, sixth paragraph. We construe the disputed limitation to cover the corresponding structure described in Appellants’ Specification and Appeal 2009-008764 Application 11/346,736 10 its equivalents. See In re Donaldson Co., Inc., 16 F.3d 1189, 1195 (Fed. Cir. 1994) (en banc). Accordingly, Cutts need not disclose the exact structure disclosed in Appellants' Specification to anticipate independent claim 17. Independent claim 17 is anticipated by Cutts as long as Cutts discloses an equivalent structure. Appellants’ Specification discloses that: [l]ogic device 36 in accordance with embodiments of the invention accepts all externally generated interrupts, e.g., from I/O adapters 14 and 16 or from other computer slices, and whenever possible passes the interrupts to each processor at times when the processors are most likely to be at the same C- point. Spec. 7, ¶ [0028]. We find that Appellants’ Specification discloses the logic device as the structure that presents an interrupt request. Similarly, Cutts disclosure teaches that the first interrupt circuit located within the first processor is capable of sending interrupts to a second processor. (FF 3.) Consequently, since Cutts’ first interrupt circuit is capable of presenting an interrupt request to the first processor, and also capable of sending an interrupt to a second processor (id), we find that Cutts’ first interrupt circuit is tantamount to an equivalent structure that performs the same function of presenting an interrupt request as Appellants’ logic device. Thus, we find that the Cutts teaches the disputed limitation. It follows that Appellants have not shown that the Examiner erred in finding that Cutts anticipates independent claim 17. Claims 18 through 20 Appellants do not provide separate arguments for patentability with respect to dependent claims 18 through 20. Therefore, we group the claims Appeal 2009-008764 Application 11/346,736 11 together and select independent claim 17 as representative of the cited claims. Consequently, Appellants have not shown error in the Examiner’s rejection of dependent claims 18 through 20 for the reasons set forth in our discussion of independent claim 17. See 37 C.F.R. § 41.37(c)(1)(vii). V. CONCLUSION OF LAW Appellants have not shown that the Examiner erred in rejecting claims 1 through 5, 7 through 9, 12 through 15, and 17 through 20 as being anticipated under 35 U.S.C. § 102(b). VI. DECISION We affirm the Examiner’s decision to reject claims 1 through 5, 7 through 9, 12 through 15, and 17 through 20 as being anticipated under 35 U.S.C. § 102(b). No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). AFFIRMED erc Copy with citationCopy as parenthetical citation