Ex Parte Klaiber et al

Board of Patent Appeals and Interferences

Sep 13, 2010

11066920 (B.P.A.I. Sep. 13, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte ALEXANDER C. KLAIBER and MICHAEL S. GRESKE
____________

Appeal 2009-002265
Application 11/066,920
Technology Center 2100
____________

Before JOSEPH L. DIXON, LANCE LEONARD BARRY, and
JEAN R. HOMERE, Administrative Patent Judges.

BARRY, Administrative Patent Judge.

DECISION ON APPEAL 1

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.

Appeal 2009-002265
Application 11/066,920

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STATEMENT OF THE CASE
The Patent Examiner rejected claims 1-10 and 13-22. The Appellants
appeal therefrom under 35 U.S.C. § 134(a). We have jurisdiction under
35 U.S.C. § 6(b).

INVENTION
The Appellants describe the invention at issue on appeal as "related
to . . . virtualization of exception handling." (Spec. 1, ¶ [0002].)

ILLUSTRATIVE CLAIM
17. A computer accessible storage medium storing a plurality of
instructions including instructions which, when executed in a
processor:
disable circuitry external to the processor from causing
an external interrupt to the processor, the circuitry
configured to cause the external interrupt responsive to
an error signal asserted by the processor, wherein the
error signal is asserted by the processor in response to
detecting an exception associated with execution of one
of a subset of instructions executable by the processor;
and
enable an intercept in the processor of a freeze event
during execution of a guest, wherein the freeze event is
detected by the processor responsive to the error, a lack
of an assertion of an ignore error indication associated
with the subset of instructions, and an attempt to execute
one of the subset of instructions.

Appeal 2009-002265
Application 11/066,920

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REJECTION
Claims 1-10 and 13-22 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over U.S. Patent No. 5,134,693 ("Saini"); U.S. Patent
No. 5,826,084 ("Brooks"); and the Appellants' Admitted Prior Art
(Specification submitted 02/25/2005, page 2, paragraph [0007]) ("AAPA").

CLAIMS 1-10, 13-17, 19, AND 21
Based on the Appellants' arguments, we will decide the appeal of
claims 17 and 21 based on claim 21 alone. See 37 C.F.R. § 41.37(c)(1)(vii).

ISSUES
Regarding independent claims 1 and 9 and representative claim 17,
the Examiner finds that "Brooks explicitly recites the concept of receiving
an interrupt from an external source [Brooks, col. 3, lines 14-19] . . . ."
(Ans. 18.) The Appellants argue that "Brooks teaching that external
interrupt signals may be input to the processor has no relevance to the
recited features." (Reply Br. 5.)
Regarding dependent claim 19, the Examiner finds that Saini discloses
"an interrupt mask register included in the external circuitry [col. 7, lines 34-
38; a control word register includes information about which exceptions
should be masked]." (Ans. 13.) The Appellants argue that "the mask bits
are in a register in Saini's processor . . . ." (App. Br. 10.)
Therefore, the issues before us are (1) whether the Examiner erred in
finding that Brooks teaches a processor transmitting an error output signal
external to itself as required by independent claims 1 and 9, (2) whether the
Examiner erred in finding that Brooks teaches or a processor receiving an
Appeal 2009-002265
Application 11/066,920

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external interrupt as required by representative claim 17, and (3) whether the
Examiner erred in finding that Saini teaches an interrupt mask register
included in circuitry external to the processor as required by dependent
claim 19.

FINDINGS OF FACT
Saini discloses a "32-bit microprocessor 60 that includes a floating-
point unit 78." (Col. 4, ll. 26-28.)
Brooks discloses "[a] microprocessor (26) [that] may multi-task a
plurality of programs, and those programs include a virtual program (38 or
40) operable in a virtual mode and a monitor program (34) operable using
protected mode semantics." (Abstract, ll. 1-5.)

ANALYSIS
The question of obviousness is "based on underlying factual
determinations including . . . what th[e] prior art teaches explicitly and
inherently . . . ." In re Zurko, 258 F.3d 1379, 1383 (Fed. Cir. 2001)
(citations omitted).
Regarding claims 1, 9, and 17, the disclosure of Brooks relied on by
the Examiner follows. "The microprocessor includes input circuitry for
receiving an external interrupt request signal corresponding to an external
interrupt directed to the virtual program, and additional input circuitry for
receiving an external interrupt number corresponding to the external
interrupt directed to the virtual program." (Col. 3, ll. 14-19.) The Examiner
summarizes this disclosure as "the concept of receiving an interrupt from an
external source . . . ." (Ans. 18.)
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We agree with the Appellants, however, that "the fact that Brooks
teaches a processor receiving another type of interrupt (external to the
processor) has nothing to do with the processor transmitting an error
signal external to the processor as recited in claim 1" (Reply Br. 5) and
claim 9. In contrast, we are persuaded that such a teaching constitutes
receiving an external interrupt as required by claim 17.
Regarding claim 19, the disclosure of Saini relied on by the Examiner
describes the "control word ('CW') register 361" (col. 7, l. 31) of the
reference's floating point unit. More specifically, the reference explains that
"[t]he control word in CW register 361 is a user-defined specification as to
how the user would like the instructions executed. For example, CW
register 361 includes information about which, if any, of the exceptions
should be masked." (Id. at ll. 34-39.)
This part of Saini does describe a mask register. We agree with the
Appellants, however, that "the mask bits are in a register in Saini's
processor, and thus are not external circuitry that controls the ignore error
input signal." (App. Br. 10.)
The Examiner does not show that the addition of Saini cures the
aforementioned deficiency of Brooks regarding claims 1 and 9. Nor does he
show that the addition of Brooks cures the aforementioned deficiency of
Saini regarding claim 19. Based on the aforementioned facts and analysis,
we conclude that the Examiner erred in finding that Brooks teaches a
processor transmitting an error output signal external to itself as required by
independent claims 1 and 9 and in finding that Saini teaches an interrupt
mask register included in circuitry external to the processor as required by
dependent claim 19. We also conclude that the Examiner did not err in
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finding that Brooks teaches a processor receiving an external interrupt as
required by representative claim 17 and claim 21, which falls therewith.

CLAIMS 18 AND 22
Regarding claim 18, the Examiner finds that "Brooks clearly discloses
. . . that a virtual program (also known as a guest) is executed [col. 3, lines
11-14] . . . ." (Ans. 26.) The Appellants argue that "these teachings fail to
teach or suggest 'the instructions, when executed, start the guest executing
on the processor.'" (Reply Br. 10.)
Regarding claim 22, the Examiner finds that the "virtual program is
exited so that the interrupt vector may be executed and the interrupt is
presented to the virtual program." (Ans. 29.) The Appellants argue that
"[t]he interrupt handling circuit passes an interrupt to the virtual program
without any guest exit occurring." (Reply Br. 11.)

ISSUES
Therefore, the issue before us are (1) whether the Examiner erred in
finding that Brooks would have suggested instructions that, when executed,
start a guest executing on the processor as required by claim 18 and (2)
whether the Examiner erred in finding that Brooks would have suggested
instructions executed in response to a guest exit that inject an interrupt into
the guest as required by claim 22.

FINDINGS OF FACT
As previously mentioned, Brooks discloses "[a] microprocessor (26)
[that] may multi-task a plurality of programs . . . ." (Abstract, ll. 1-2.)
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ANALYSIS
"'Every patent application and reference relies to some extent upon
knowledge of persons skilled in the art to complement that disclosed . . . .'"
In re Bode, 550 F.2d 656, 660 (CCPA 1977) (quoting In re Wiggins, 488
F.2d 538, 543 (CCPA 1973)). Those persons "must be presumed to know
something" about the art "apart from what the references disclose." In re
Jacoby, 309 F.2d 513, 516 (CCPA 1962).
Regarding claim 18, the passage of Brooks relied on by the Examiner
discloses that the plurality of programs that may be multi-tasked by
microprocessor 26 "include a virtual program operable in a virtual mode . . .
." (Col. 3, ll. 12-13.) The Examiner's finding that the virtual program
constitutes a guest program is uncontested. "Silence implies assent."
Harper & Row Publishers, Inc. v. Nation Enters., 471 U.S. 539, 572 (1985).
We agree with the Examiner that persons skilled in the art would have
known that "the virtual (also known as guest) software cannot start
executing unless instructions (of the virtual software) are executed." (Ans.
26.) Based on the aforementioned facts and analysis, we conclude that the
Examiner did not err in finding that Brooks would have suggested
instructions that, when executed, start a guest executing on the processor as
required by claim 18.
"The Patent Office has the initial duty of supplying the factual basis
for its rejection. It may not . . . resort to speculation, unfounded assumptions
or hindsight reconstruction to supply deficiencies in its factual basis." In re
Warner, 379 F.2d 1011, 1017 (CCPA 1967).
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Regarding claim 20, the passage of Brooks relied on by the Examiner
discloses that "once these semantics are used to prepare the interrupt
handler, the hardware presents the interrupt to the virtual 8086 program as
the recipient of the interrupt; in other words, the hardware executes the
interrupt vector and then directly resumes the virtual 8086 program upon
completion of that interrupt handler." (Col. 9, ll. 5-11.) The passage does
not mention exiting the virtual 8086 program. We will not resort to
speculation or unfounded assumptions to supply such a teaching. We note
that: the program need not be exited to execute the interrupt vector; it may
merely be paused. The Examiner does not show that the addition of Saini
cures the aforementioned deficiency of Brooks. Based on the
aforementioned facts and analysis, we conclude that the Examiner erred in
finding that Brooks would have suggested instructions executed in response
to a guest exit that inject an interrupt into the guest as required by claim 22.

CLAIM 22
The Examiner finds that "because the interrupt flag of [Brooks] is
used to override the signals, it is used 'instead' of them." (Ans. 25.) The
Appellants argue that "[t]he interrupt flag is not used instead of the signals
from the floating point coprocessor . . . ." (App. Br. 11.)

ISSUE
Therefore, the issue before us is whether the Examiner erred in
finding that Brooks teaches ignoring an external signal and instead use an
internal indication generated internally by the processor as required by
claim 22.
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FINDINGS OF FACT
The Examiner relies on the following teachings of Brooks to support
his finding.
[I]n various microprocessors certain external interrupts are
maskable as known in the art; that is, depending on other
aspects of the microprocessor, it may be that the asserted
external interrupt is masked from interrupting the
microprocessor (i.e., the interrupt request is simply ignored).
For example, this operation may occur with respect to the
interrupt flag ("IF") bit.
(Col. 6, ll. 47-53.)
Specifically, and as is known, current INTEL 80x86
microprocessors include an IF bit in the Eflags register of the
microprocessor. If the IF bit is set in a given state (e.g., a logic
0), then any maskable external interrupt arriving on the INTEL
pin will be ignored by the INTEL microprocessor.
(Col. 9, ll. 53-59.)

ANALYSIS
The IF bit does instruct various microprocessors to ignore maskable
external interrupt signals. We agree with the Appellants, however, that the
IF bit "is not used instead of the [external interrupt] signals . . . but rather in
conjunction with the signals. That is, if the interrupt flag is clear, then the
signals are masked but if the interrupt flag is set, the signals have an effect.
(App. Br. 11.)

The Examiner does not show that the addition of Saini cures the
aforementioned deficiency of Brooks. Based on the aforementioned facts
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and analysis, we conclude that the Examiner erred in finding that Brooks
teaches ignoring an external signal and instead use an internal indication
generated internally by the processor as required by claim 22.

DECISION
We reverse the rejection of claims 1-10, 13-16, 19, 20, and 22. In
contrast, we affirm the rejection of claims 17, 18, and 21.
No time for taking any action connected with this appeal may be
extended under 37 C.F.R. § 1.136(a)(1). See 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

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