Ex Parte Kimelman et al

Board of Patent Appeals and Interferences

Mar 30, 2010

11032226 (B.P.A.I. Mar. 30, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________
Ex parte PAUL KIMELMAN
and RICHARD ROY GRISENTHWAITE
____________
Appeal 2009-010701
Application 11/032,2261
Technology Center 2100
____________
Decided: March 31, 2010
____________
Before LEE E. BARRETT, HOWARD B. BLANKENSHIP, and
DEBRA K. STEPHENS, Administrative Patent Judges.

BARRETT, Administrative Patent Judge.

DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) from the final
rejection of claims 1-24. Claims 25 and 26 have been canceled. We have
jurisdiction pursuant to 35 U.S.C. § 6(b).
An oral hearing was held on March 24, 2010.
We reverse.

1 Filed January 11, 2005, titled "Management of Polling Loops in a
Data Processing Apparatus." The real party in interest is ARM Limited.
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STATEMENT OF THE CASE
The invention
The invention relates to managing polling loops. The description of
the prior art describes that it is becoming more common for data processing
systems to include processing units in addition to the main processing unit or
central processing unit (CPU). Examples of such additional hardware units
or subsidiary processing units are data accelerators such as those used to
perform certain video processing functions, direct memory access (DMA)
controllers, liquid crystal display (LCD) controllers, etc. When the main
processing unit delegates a particular task to one of the subsidiary processing
units, one way to determine when that task has been completed is to arrange
the subsidiary processing unit to set a flag when it has completed the task,
and for the main processing unit to periodically poll that flag in order to
determine whether the flag has been set, and accordingly determine whether
the task has been completed. One problem with this approach is that the
main processing logic may need to poll the flag a significant number of
times and in systems where low power consumption is desirable, this
repeated polling is undesirable. Another problem is that the memory in
which the flags are maintained is accessible by a common bus
interconnecting the main processing unit, subsidiary processing unit(s), and
memory. Therefore, every time the main processing unit wants to poll the
flag, it needs to request access to the bus which increases the likelihood of
contention among the processing units seeking access to the bus. Spec. 1.
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Appellants' Figure 1 shows a main processing unit 20 coupled via a
bus 55 to subsidiary processing units (e.g., DMA controller 30, data
accelerator 40, and LCD controller 50), and to a memory 80. The main
processing unit 20 can delegate tasks to one of the subsidiary processing
units, but it needs to know when the task is completed. To achieve this, each
of the units 30, 40, 50 has a corresponding completion flag field 82, 84, 86
in the memory 80 and when a particular processing unit completes a task
allocated to it, it sets its associated completion flag. Spec. 7, l. 27 to Spec. 9,
l. 8. The subsidiary processing units 30, 40, 50 have associated interrupt
paths 32, 42, 52 over which it may issue an interrupt signal to the main
processing unit 20. Spec. 9, ll. 9-13. In one embodiment, each of the
subsidiary processing units 30, 40, 50 is arranged to issue an interrupt when
it completes execution of a task. Spec. 9, ll. 24-25.
The prior art problem of polling is alleviated by arranging the main
processing unit 20 to enter a power saving mode if, on polling the
completion field a threshold number of times, it is determined that the task
has not been completed. This avoids repetition of the polling loop
unnecessarily. Each subsidiary processing unit is arranged to issue a
notification to the main processing unit when it has completed execution of
the task, and receipt of this notification causes the main processing unit to
exit the power saving mode. Spec. 10, ll. 10-18. In one embodiment, since
the notification is not unique to a subsidiary processing unit, upon exiting
the power saving mode, the main processing unit is arranged to poll the
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completion flag of interest in order to determine whether the relevant task
has been completed. Spec. 13, ll. 14-25.

Illustrative claim
Claim 1 is reproduced below for illustration:

1. A data processing apparatus comprising:
a main processing unit;
a subsidiary processing unit configured to perform a task on
behalf of the main processing unit;
the subsidiary processing unit being configured to set a
completion field when said task has been completed and the main
processing unit being configured to poll the completion field in order
to determine whether said task has been completed;
if on polling the completion field a threshold number of times
the main processing unit determines that the task has not been
completed, the main processing unit being configured to enter a power
saving mode;
the subsidiary processing unit being configured, when said task
has been completed, to cause a notification to be issued on a path
interconnecting the main processing unit and the subsidiary
processing unit;
the main processing unit being configured, upon receipt of said
notification, to exit said power saving mode.

The reference

Townsley US 5,623,677 Apr. 22, 1997

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The rejection
Claims 1-24 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Townsley.

ISSUES
The issues, as argued, are:
Issue 1: Does Townsley teach "if on polling the completion field a
threshold number of times the main processing unit determines that the task
has not been completed, the main processing unit being configured to enter a
power saving mode," as recited in claim 1?
Issue 2: Does Townsley teach "the subsidiary processing unit being
configured, when said task has been completed, to cause a notification to be
issued on a path interconnecting the main processing unit and the subsidiary
processing unit," as recited in claim 1?
Claim 13 contains corresponding limitations, so claim 1 is taken as
representative. Appellants also argue the separate patentability of dependent
claims 2, 3, 5-7, 14, 15, and 17-19 (Br. 14-15), but we find it unnecessary to
address these arguments.

PRINCIPLES OF LAW
"Anticipation requires the presence in a single prior art disclosure of
all elements of a claimed invention arranged as in the claim." Connell v.
Sears, Roebuck & Co., 722 F.2d 1542, 1548 (Fed. Cir. 1983).

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FINDINGS OF FACT
Townsley relates to reducing power consumption of a processor in a
computer system. Col. 2, ll. 61-62.
The hardware arrangement is shown in Figure 1. The operating
system checks the status of the processor 12 periodically to determine
whether processor 12 is actively processing programs or remains in an
inactive state waiting for data to be transferred to it for processing. Col. 7,
ll. 23-30. A signal is sent to control logic when the processor is in the
inactive state. The control logic 11 generates two signals, one to a phase-
locked loop (PLL) 6 that clocks the processor and a second to a switch 23
that connects the processor 12 to the power supply 15. The signals from the
control logic disable the clock signals to the processor 12 and then decouple
the power supply to the processor when the processor is in the inactive state.
The clock signals from the PLL to the processor are disabled while the PLL
maintains synchronization. Col. 7, ll. 30-54. This avoids the latencies
involved when a PLL is turned off and back on. Col. 2, ll. 33-40.
The control logic also controls the switch and the PLL to couple the
processor to the power supply and then enable the clock signals in response
to a periodic interrupt signal, a non-periodic interrupt, or a bus request from
a peripheral device. Col. 3, ll. 10-14. The periodic power-on interval allows
the processor 12 to poll the peripheral devices coupled to the input/output
(I/O) interface unit 14 and to perform other operating system tasks which
may need periodic updating. Col. 7, ll. 55-66; col. 9, ll. 15-18. Thereafter,
the programming structure signals the control logic again when it determines
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that the processor again reenters an inactive state, such that the control logic
disables the clock signals and decouples the power supply to the processor
until the next interrupt or bus request. Col. 9, ll. 51-67.
Figure 3 shows the process for setting or clearing the idle bit. When
the idle bit is set (step 307), the processor is inactive, and when the idle bit is
cleared (step 308, where "Set" should be "Clear"), the processor is active.
Figure 2 shows the process for the processor entering the power save
mode (step 209) based on the status of the idle bit (step 205) and other
conditions (steps 206 and 207).

ANALYSIS
Issue 1
Appellants argue that Townsley repeatedly describes that the
processor should enter the power saving mode only if the processor is
inactive, and there is no teaching of entering a power saving mode "if on
polling the completion field a threshold number of times the main processing
unit determines that the task has not been completed." Br. 8. It is argued
that the Examiner's finding that step 205 of Figure 2 shows entering a power
saving mode based upon the polling step is in error because "the polling
activity itself does not control entry into the power saving mode of
operation; it can only prevent the power saving mode from being entered,
i.e., by clearing the idle bit." Br. 9. It is argued that the Examiner also errs
in implying that if the polling process at step 204 indicates that the status of
the polled device has not changed, then the power saving mode is entered,
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because setting the idle bit has nothing to do with the polling activity.
Br. 10. Appellants argue that while Figure 3 indicates a "threshold," this has
nothing to do with the threshold number of times that a completion field is
polled and Figure 3 never refers to polling. Br. 10.
The Examiner's most complete statement regarding the limitation "if
on polling the completion field a threshold number of times the main
processing unit determines that the task has not been completed, the main
processing unit being configured to enter a power saving mode" is:
Note that specification does not explicitly define "enter" power saving
mode. Therefore, Examiner construes "enter" power saving mode to
include executing vital steps of powering down CPU in order to avoid
high latency, data lose [sic, loss], and damages in the system.
Townsley does "enter" power saving mode as shown in steps 204,
205, 206, 207, 208, and 209 in order to avoid high latency responds to
late-arriving interrupts and saves processor state from register RAM
to avoid data lose. These steps are executed based on polling the
peripheral devices, column 10, lines 18-22. The extra steps are part of
entering the power saving mode, as construed above, (i.e. checking
the idle bits 205, and steps 206-209 in order to avoid high latency,
data lose [sic], and system damages.) In addition, Genentech, Inc. v.
Chiron Corp., 112 F.3d 495, 501, 42 USPQ2d 1608, 1613 (Fed. Cir.
1997) ("Comprising" is a term of art used in claim language which
means that the named elements are essential, but other elements may
be added and still form a construct within the scope of the claim.)

Ans. 10-11.
Appellants argue that this interpretation is inconsistent with the plain
and ordinary meaning of "enter," which requires actually entering a power
saving mode and not just doing something in anticipation of entering the
power saving mode. Reply Br. 2. It is argued that Figure 3 of Townsley
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describes a particular sequence of events completely unrelated to polling
peripheral devices that must be followed to set the idle bit at step 307.
Reply Br. 3. It is argued again that a power saving mode is only entered if it
is determined that the processor is in an inactive state and never for the
condition claimed, i.e., after "polling the completion field a threshold
number of times, the main processing unit determines that the task has not
been completed." Reply Br. 4, 6. Appellants argue that the mere reference
to polling in 204 of Figure 2 does not mean that the processor enters the
power saving mode upon polling a number of times. Reply Br. 4.
We agree with Appellants' arguments. It is abundantly clear from
Townsley that the processor is put in the power saving mode solely based on
the condition that the processor is no longer actively processing a program
and is inactive. See, e.g., Abstract; col. 2, ll. 65 & 66; col. 3, ll. 7, 16-17, 38;
col. 6, ll. 31-32; col. 7, ll. 29 & 31; col. 8, ll. 46-48 & 55-56; col. 10,
ll. 20-22 & 41, etc. Thus, we assume that the Examiner's rejection is based
on a special claim interpretation. However, we do not see a reasonable
claim interpretation which reads on Townsley.
As to the Examiner's statement that the "Examiner construes 'enter'
power saving mode to include executing vital steps of powering down CPU
in order to avoid high latency, data lose [sic], and damages in the system"
(Ans. 10), we agree that entering a power saving mode requires powering
down the CPU. We do not agree that the reason for powering down is "to
avoid high latency, data lose [sic, loss], and damages in the system"
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(Ans. 10) which the Examiner repeats later in the paragraph, since the reason
is to save power, but do not hold these statements to be cause for reversal.
The limitation "if on polling the completion field a threshold number
of times the main processing unit determines that the task has not been
completed, the main processing unit being configured to enter a power
saving mode" requires that entering a power saving mode is based on the
condition "if on polling the completion field a threshold number of times the
main processing unit determines that the task has not been completed." As
best we understand the rejection, the Examiner finds that step 204 in
Figure 2 shows polling a completion field a threshold number of times (i.e.,
once) and if the status is not changed (indicating that the task has not been
completed), the idle bit remains set (indicating the processor is inactive,
assuming the idle bit was previously set) and the processor may enter the
power save mode through steps 206-209. The Examiner interprets that the
claim does not preclude other conditions (which the Examiner calls "extra
steps") in addition to polling because of the transition word "comprising."
Thus, Figure 2 of Townsley shows entering a power saving mode at step 209
after a series of steps 204-208, including a step 204 of polling peripheral
devices, and the Examiner finds that "[t]hese steps are executed based on
polling the peripheral devices . . . . The extra steps are part of entering the
power saving mode . . . ." Ans. 11.
We do not agree with this analysis. Townsley teaches that the
processor is put in the power saving mode based on the condition that the
processor is no longer actively processing a program and is inactive. If the
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processor is active the idle bit is cleared and if it is inactive the idle bit is set.
Figures 2 and 3 do not support the Examiner's position that entering the
power saving mode is based on polling. Figure 3 shows that the idle bit is
set (step 307, indicating the processor is inactive) when a counter exceeds a
certain threshold (block 306), where the counter is incremented when the
processor is inactive (col. 11, ll. 14-30); if the counter is less than the
threshold, the processor is active and the idle bit is cleared (block 308 should
be "Clear Idle Bit" instead of "Set Idle Bit"). Thus, the idle bit is set or
cleared solely on the condition that the processor is inactive or active,
respectively, and the status of the idle bit determines whether the processor
enters the power save mode as shown in Figure 2.
Block 204 in Figure 2 describes polling a peripheral device and
clearing the idle bit if the status of the polled device has changed, indicating
the processor is active; if not, the idle bit remains set indicating that the
processor is still inactive. The decision, at the following block 205, as to
whether to resume normal operation ("NO" output) or to proceed to
steps 206-209 to possibly enter a power save mode ("YES" output) is based
solely on the status of the idle bit. The polling step 204 can only clear the
idle bit, indicating that the processor is active. If the polling step 204
indicates that the status of the polled device has not changed, which might
be considered to indicate "that the task has not been completed" as claimed
(assuming there is an assigned task), the polling step does nothing to alter
the idle bit or require that the processor enter the power save mode. We
agree with Appellants' description of Townsley that "[a]s long as the main
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processor 12 is in an active mode of operation, it polls the completion field"
(Br. 12) and "Townsley does not even contemplate the possibility of entering
a power saving mode when the main processing unit is inactive" (Br. 13).
For these reasons, we find that Townsley's processor does not enter a power
save mode based on the condition "if on polling the completion field a
threshold number of times the main processing unit determines that the task
has not been completed."

Issue 2
The Examiner finds that Townsley teaches a notification to be issued
because it teaches interrupts, referring to column 7, lines 1-22, column 9,
lines 28-30. Ans. 12-13.
Appellants argue that the periodic interrupt in Townsley wakes up the
main processor after which it can perform polling, but this interrupt has
nothing to do with receiving a notification when the subsidiary processing
unit has completed its task. Br. 11. It is argued that the other interrupts can
cause the main processor to wake up, but there is no disclosure of causing a
subsidiary processing unit that is handling a task on behalf of the main
processing unit to issue a notification to cause it to exit the power save
mode. Br. 11-12. It is argued that there is no need for the claimed wake up
mechanism in Townsley because Townsley is not concerned with entering a
power save mode to avoid excessive polling. Br. 12-13.
We agree with Appellants. In the limitation "the subsidiary
processing unit being configured, when said task has been completed, to
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cause a notification to be issued on a path interconnecting the main
processing unit and the subsidiary processing unit," the "task" is defined as
"a task on behalf of the main processing unit" performed by the subsidiary
processing unit, not just any task performed by a device, which detail is not
addressed in the rejection. The rejection relies on the periodic interrupt
described at column 7, but this interrupt only wakes up the computer so it
can poll devices and is not associated with any device finishing a task.
There is no teaching that the regular interrupts in Townsley are generated by
devices which are performing "a task on behalf of the main processing unit"
and that notification is issued when "said task has been completed."
Nevertheless, even if the devices are performing tasks on behalf of the
processor, there is no connection with the processor entering a power save
mode when polling indicates that a task is incomplete and the device issuing
a notification when that task is complete.

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CONCLUSION
Townsley does not teach either "if on polling the completion field a
threshold number of times the main processing unit determines that the task
has not been completed, the main processing unit being configured to enter a
power saving mode" (Issue 1) or "the subsidiary processing unit being
configured, when said task has been completed, to cause a notification to be
issued on a path interconnecting the main processing unit and the subsidiary
processing unit" (Issue 2). The rejection of the dependent claims falls with
the rejection of independent claims 1 and 13. Accordingly:
The rejection of claims 1-24 under 35 U.S.C. § 102(b) is reversed.

REVERSED

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