Ex Parte Kim

Board of Patent Appeals and Interferences

Dec 16, 2009

10840374 (B.P.A.I. Dec. 16, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
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Ex parte MIN-SU KIM
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Appeal 2009-004075
Application 10/840,3741
Technology Center 2100
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Decided: December 16, 2009
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Before JEAN R. HOMERE, JAY P. LUCAS, and JOHN A. JEFFERY,
Administrative Patent Judges.

HOMERE, Administrative Patent Judge.

DECISION ON APPEAL

1 Filed on May 7, 2004. This application claims foreign priority to 2003-
50123, which was filed on July 22, 2003. The real party in interest is
Samsung Electronics Co., Ltd. (App. Br. 3.)
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I. STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) (2002) from the
Examiner’s final rejection of claims 7, 8, 20, and 21. (App. Br. 3.)2 Claims
1 through 6, 10 through 19, and 22 through 24 have been withdrawn from
consideration. (Id.) Claim 9 has been cancelled. (Id.) We have jurisdiction
under 35 U.S.C. § 6(b) (2008).
We affirm.
Appellant’s Invention
Appellant invented an apparatus having a plurality of threads that
operate in separate thread memories. (Spec. 1, Para. [0002].) Appellant’s
Figure 6A depicts a tag portion of a translation lookaside buffer (“TLB”)
that includes a process identification (“ID”), a thread ID, a thread bit, a
virtual page number, and a page offset including a valid field (“V”) and lock
field (“L”). (Id. at 10, Para. [0042].) Further, the data portion of the TLB
includes a physical page number and associate protection. (Id. at 10, Para.
[0043].) According to Appellant, the claimed invention prevents memory
collision between threads and program protection problems and, further,
reduces the effort required to manage memory during programming. (Id. at
12, Para. [0048].)
Illustrative Claim
Independent claim 7 further illustrates the invention as follows:

7. A translation lookaside buffer of a microprocessor,
comprising:

2 All references to the Appeal Brief are to the Appeal Brief filed on January
25, 2008, which replaced the prior Appeal Brief filed on December 11,
2007.
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a tag unit that includes a thread ID, a virtual memory
page number and a thread bit, the thread bit being for
determining whether a virtual memory address is an address for
a process memory or a thread memory; and

a data unit including a physical memory page number,
the data unit corresponding to the tag unit and used to translate
a virtual memory address into a physical memory address.

Prior Art Relied Upon
The Examiner relies on the following prior art as evidence of
unpatentability:
Dean 6,442,585 B1 Aug. 27, 2002
Joy 2002/0138717 A1 Sep. 26, 2002
Chaudhry 2003/0056020 A1 Mar. 20, 2003

Applicant Admitted Prior Art [hereinafter “AAPA”]
Rejection on Appeal
The Examiner rejects the claims on appeal as follows:
Claims 7, 8, 20, and 21 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over the combination of AAPA, Chaudhry, Dean, and
Joy.
Appellant’s Contentions
Appellant contends that Joy’s disclosure of disabling thread ID
tagging does not inherently teach a thread bit and, therefore, fails to teach “a
thread bit for determining whether a virtual memory address is an address
for a process memory or a thread memory,” as recited in independent claim
7. (App. Br. 6-8; Reply Br. 5-6.) Further, Appellant alleges that Joy’s
disclosure fails to teach the disputed limitation because Joy defines a
lightweight process as a simplified, minimal-context process or thread.
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(App. Br. 8-9; Reply Br. 4-5.) Therefore, Appellant argues, if the thread ID
is disabled, the lightweight process may still constitute a thread. (Id.)
Additionally, Appellant contends that there is insufficient rationale for the
proffered combination. (App. Br. 10-21.)
Examiner’s Findings and Conclusions
The Examiner finds that Joy’s disclosure of a thread identification
(“TID”) bit teaches a thread bit as claimed. (Ans. 9.) In particular, the
Examiner finds that Joy’s disclosure of enabling and disabling thread ID
tagging when processing threads and lightweight processes, respectively,
teaches the disputed limitation. (Id. at 8-9.) The Examiner also finds that
“…a process memory or a thread memory” is claimed in the alternative and,
therefore, Joy’s disclosure of a TID teaches identifying a thread. (Id. at 9;
11-12). Further, the Examiner finds that “the functional recitation of ‘the
thread being for determining…’ does not differentiate the claimed invention
from the prior art.” (Id. at 9-10.) Additionally, the Examiner finds that there
is sufficient rationale for the proffered combination. (Id. at 12-17.)

II. ISSUE
Has Appellant shown that the Examiner erred in concluding that the
combination of AAPA, Chaudhry, Dean, and Joy renders independent claim
7 unpatentable? In particular, the issue turns on whether:
a) the proffered combination teaches “[a] thread bit being for
determining whether a virtual memory address is an address for a process
memory or a thread memory,” as recited in independent claim 7; and
b) there is sufficient rationale for the proffered combination.

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III. FINDINGS OF FACT
The following Findings of Fact (“FF”) are shown by a preponderance
of the evidence.
AAPA
1. Appellant’s Figure 2A depicts a conventional TLB which
includes “a process ID, a virtual page number, and a page offset, including a
[V] and [L] parameter and the data portion may include a physical page
number and protection such as access permission.” (Spec. 4, Para. [0012].)
Chaudhry
2. Chaudhry generally relates to facilitating interprocessor
communication and synchronization through a hardware message buffer.
(Pg. 1, Para. [0003].) Chaudhry’s Figure 2 depicts a translation table (202)
that includes a number of entries. (Pg. 3, Para. [0043].) “Each of these
entries contain[s] a number of fields, including a thread identifier (204). . . .
Thread identifier (214) identifies a specific thread or process/context.” (Id.)
Dean
3. Dean generally relates to measuring the performance of
computer systems and, in particular, to scheduling execution contexts
according to the measured performance. (Col. 1, ll. 57-60.) Dean’s Figure 2
depicts a TLB (240), a trigger function (250), a counter (265), a selection
function (260), sampling buffers (300-302), and sampling software (280).
(Col. 4, ll. 38-41.) “During operation of the system, transaction input (241)
is presented to the . . . TLB (240) on line (241). The transaction input can
include a virtual address (“VA”), a context identifier such as an address
space number (“ASN”), and in the case of multi-threaded processor design, a
hardware context identifier (“HCI”).” (Col. 4, ll. 42-47.)
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4. Dean’s Figure 3 depicts that “[t]he context field (330) can store
the ASN, the . . . HCI in case of a multi-threaded processor, a process
identifier (“PID”), and/or a thread identifier (“TID”) of the source of the
memory transaction when the source is an instruction execution in the
processor pipeline.” (Col. 8, ll. 17-22.)
Joy
5. Joy generally relates to processor or computer architecture and,
in particular, to multiple-threading processor architectures and methods of
operation and execution. (Pg. 1, Para. [0002].) Joy discloses that “[o]ne
technique for cache segregation utilizes logic for storing and communicating
[TID] bits. For example, the TID bits can be inserted at the most significant
bits of the cache index.” (Pgs. 9-10, Para. [0111]. Further, Joy’s Figure 8
depicts that “[t]he cache index (812) is configured to include a [TID] (823)
and index bits field (824). (Pg. 10, Para. [0112].)
6. Joy’s figure 6 depicts that
[t]he logic supporting native threads and lightweight processes
includes logic that disables [TID] tagging and disables cache
segregation since lightweight processes and native threads share
the same virtual address space. The thread switch logic (610)
accommodates lightweight processes by disabling [TID]
tagging and cache segregation, advantageously avoiding
allocation of cache and other resources to threads that do not
utilize the resources.

(Id. at Para. [0114].)

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IV. PRINCIPLES OF LAW
Obviousness
“On appeal to the Board, an applicant can overcome a rejection [under
§ 103] by showing insufficient evidence of prima facie obviousness or by
rebutting the prima facie case with evidence of secondary indicia of
nonobviousness.” In re Rouffet, 149 F.3d 1350, 1355 (Fed. Cir. 1998)
(citations omitted).
Section 103 forbids issuance of a patent when “the differences
between the subject matter sought to be patented and the prior art are
such that the subject matter as a whole would have been obvious at
the time the invention was made to a person having ordinary skill in
the art to which said subject matter pertains.”

KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007).
In KSR, the Supreme Court emphasized "the need for caution in
granting a patent based on the combination of elements found in the prior
art," and discussed circumstances in which a patent might be determined to
be obvious. Id. at 415 (citing Graham v. John Deere Co., 383 U.S. 1, 12
(1966)). The Court reaffirmed principles based on its precedent that "[t]he
combination of familiar elements according to known methods is likely to be
obvious when it does no more than yield predictable results." Id. at 416.
The operative question in this "functional approach" is thus "whether the
improvement is more than the predictable use of prior art elements according
to their established functions." Id. at 417.
In identifying a reason that would have prompted a person of ordinary
skill in the relevant field to combine the prior art teachings, the Examiner
must show “some articulated reasoning with some rational underpinning to
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support the legal conclusion of obviousness.” Id. at 418 (quoting In re
Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006)).

V. ANALYSIS
Claim 7
Independent claim 7 recites, in relevant part, “[a] thread bit being for
determining whether a virtual memory address is an address for a process
memory or a thread memory.”
As detailed in the Findings of Fact section above, Joy discloses
multiple-threading processor architecture that utilizes logic for storing and
communicating TID bits. (FF 5.) Further, Joy discloses that the logic
disables TID tagging and cache segregation when the lightweight processes
and native threads share the same virtual address space. (FF 6.) We find
that Joy’s disclosure of logic that stores and communicates TID bits teaches
a thread ID with associate thread bits. We also find that Joy’s logic disables
TID tagging and cache segregation when it determines that both the
processes and corresponding threads occupy the same virtual memory
address. In particular, we find that an ordinarily skilled artisan would have
appreciated that utilizing Joy’s disclosure of thread bits, in conjunction with
logic that determines the virtual memory address of processes and
corresponding threads, reasonably teaches the disputed limitation.
Additionally, we note that the claimed limitation is directed to a
“thread bit being for determining whether a virtual memory address is an
address for a process memory or a thread memory” (App. Br. 23, Claims
App’x.) We agree with the Examiner that such language does not require
that the thread bit to actually determine whether a virtual memory address is
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an address for a process memory or a thread memory. (Ans. 9-10.) Rather,
it is a statement of intended use, which is fully met by a prior art structure
that is capable of performing the intended use. That is, a statement of
intended use in an apparatus claim cannot distinguish over a prior art
apparatus that discloses all recited limitations and is capable of performing
the recited function. See In re Schreiber, 128 F.3d 1473, 1477 (Fed. Cir.
1997); see Application of Dense, 156 F.2d 76 (CCPA 1946). See also Ex
parte Satchell, Appeal No. 2008-0071, 2008 WL 4828136 (BPAI 2008)
(non-precedential). Appellant’s argument is not commensurate with the
scope of the claim. Thus, we agree with the Examiner that the combination
of AAPA, Chaudhry, Dean, and Joy teaches “[a] thread bit being for
determining whether a virtual memory address is an address for a process
memory or a thread memory.” It follows that Appellant has not shown that
the Examiner erred in concluding that the combination of AAPA, Chaudhry,
Dean, and Joy renders independent claim 7 unpatentable.
Rationale to Combine
As detailed in the Findings of Fact section above, AAPA discloses a
conventional TLB which includes a process ID and a virtual page number,
and, further, a data portion including a physical page number. (FF 1.)
Chaudhry’s disclosure complements AAPA by teaching a thread identifier
that identifies a specific thread or process. (FF 2.) Further, Dean’s
disclosure complements the combination of AAPA and Chaudhry by
teaching a TLB containing context identifiers, including a TID. (FF 3-4.)
Additionally, as set forth above, Joy’s disclosure complements the
combination of AAPA, Chaudhry, and Dean by teaching thread bits, in
conjunction with logic that determines the virtual memory address of
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processes and corresponding threads. (FF 5-6.) We find that AAPA,
Chaudhry, Dean, and Joy disclose prior art elements that perform their
ordinary functions to predictably result in a TLB of a microprocessor
comprising a process ID, a thread ID, a thread bit, a virtual page number,
and, further, a data portion of the TLB which includes a physical page
number. See KSR, 550 U.S. at 418-19. Thus, Appellant’s argument that the
Examiner has not provided sufficient rationale to warrant the proffered
combination is unavailing. It follows that Appellant has failed to show that
the Examiner erred in concluding that the combination of AAPA, Chaudhry,
Dean, and Joy renders independent claim 7 unpatentable.
Claims 8, 20, and 21
Appellant does not provide separate arguments with respect to claims
8, 20, and 21. Therefore, we select independent claim 7 as representative of
the cited claims. Consequently, Appellant has not shown error in the
Examiner’s rejection of claims 8, 20, and 21 for the reasons set forth in our
discussion of independent claim 7. 37 C.F.R. § 41.37(c)(1)(vii) (2008).

VI. CONCLUSION OF LAW
Appellant has not shown that the Examiner erred in rejecting claims 7,
8, 20, and 21 as being unpatentable under 35 U.S.C. § 103(a).

VII. DECISION
We affirm the Examiner’s decision to reject claims 7, 8, 20, and 21.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2009).
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AFFIRMED

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