Ex Parte Kilian et al

Patent Trial and Appeal Board

Aug 26, 2013

11011799 (P.T.A.B. Aug. 26, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/011,799 12/13/2004 Frank Kilian 6570P174 6390
45062 7590 08/26/2013
SAP/BSTZ
BLAKELY SOKOLOFF TAYLOR & ZAFMAN
1279 Oakmead Parkway
Sunnyvale, CA 94085-4040
EXAMINER
COYER, RYAN D
ART UNIT PAPER NUMBER
2197
MAIL DATE DELIVERY MODE
08/26/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte FRANK KILIAN and JAN DOSTERT
____________________

Appeal 2011-002852
1

Application 11/011,799
Technology Center 2100
____________________

Before JEAN R. HOMERE, HUNG H. BUI, and LYNNE E. PETTIGREW,
Administrative Patent Judges.

HOMERE, Administrative Patent Judge.

DECISION ON APPEAL

1
The real party in interest is SAP AG. (App. Br. 1.)

Appeal 2011-002852
Application 11/011,799

2
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1, 2, 4, 5, 7-10, and 14-17. Claims 3, 6, 11-13, and 18-21
have been cancelled. (App. Br. 3.) We have jurisdiction under 35 U.S.C.
§ 6(b).
We affirm.
Appellants’ Invention
Appellants invented a method and system for switching between a
productive interpreter loop and a debugging interpreter loop in an
operational virtual machine (VM). (Abstr.) In particular, during the
execution of a thread including a debug event, an application programming
interface (API) switches from the productive interpreter loop to the debug
interpreter loop thereby switching from a thread execution mode to a thread
debug mode within the VM. (Spec. [0010], [0011]).

Illustrative Claim
Independent claim 1 further illustrates the invention as follows:

1. An apparatus comprising:
a virtual machine (VM) to execute a thread including a
debug event;
a processor operatively coupled to a memory, the
processor to execute the VM;
a productive interpreter loop to provide debug thread
execution on the VM;
a debugging interpreter loop to provide optimized thread
execution on the VM concurrently with the productive
interpreter loop;
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Application 11/011,799

3
an application programming interface (API) to trigger,
during the debug event, a switch from executing the thread via
the productive interpreter loop to executing the thread via the
debugging interpreter loop while the VM remains operational.

Prior Art Relied Upon
The Examiner relies on the following prior art as evidence of
unpatentability:
Blandy US 6,256,752 B1 Jul. 3, 2001
Bates US 6,587,967 B1 Jul. 1, 2003
Kalra US 2005/0132338 A1 Jun. 16, 2005
Russell US 6,988,662 B2 Jan. 24, 2006
Alpern US 7,107,578 B1 Sep. 12, 2006

Rejections on Appeal
The Examiner rejects the claims on appeal as follows:
1. Claims 1, 2, 4, 5, 14, and 15 stand rejected under 35 U.S.C. § 103(a), as
being unpatentable over the combination of Blandy and Bates.
2. Claims 7 and 16 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Blandy, Bates, and Kalra.
3. Claim 8 stands rejected under 35 U.S.C. § 103(a) as being unpatentable
over the combination of Blandy, Bates, Kalra, and Alpern.
4. Claim 9 stands rejected under 35 U.S.C. § 103(a) as being unpatentable
over the combination of Blandy, Bates, and Russell.
5. Claims 10 and 17 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Blandy, Bates, and Alpern.
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Application 11/011,799

4
ANALYSIS
We consider Appellants’ arguments seriatim as they are presented in
the Appeal Brief, pages 8-12, and the Reply Brief, pages 3-5.
Dispositive Issue: Under 35 U.S.C. § 103, did the Examiner err in
finding that the combination of Blandy and Bates teaches or suggests during
a debug event, an API triggers a switch from executing a thread in a
productive interpreter loop to executing the thread in a debugging
interpreter loop, as recited claim 1?
Appellants argue that the Examiner erred in finding that the proffered
combination teaches or suggests the disputed limitations emphasized above.
According to Appellants, Blandy discloses determining whether to execute a
thread in a debug mode prior to executing the thread, and not during the
execution of the thread, as required by the claim. (App. Br. 8-12, Reply Br.
3-4.) In response, the Examiner concludes that the claim does not require
the switching of modes to occur during an execution of a thread. According
to the Examiner, the claim merely requires switching between the two
modes during a debug event, which does not necessarily occur during the
thread execution. (Ans. 12-13.) Notwithstanding this claim construction,
the Examiner finds that Blandy’s disclosure of dynamically switching
between the two modes teaches the disputed limitations. (Ans. 13.)
On the record before us, we agree with the Examiner’s rejection of
claim 1. We note at the outset that because the claim indicates that a debug
event is included in the thread execution, the recitation of switching between
the two modes during a debug event occurs during the VM execution of the
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Application 11/011,799

5
thread. Therefore, Appellants properly argue that the claim requires the
switching between modes occurs during a thread execution.
Notwithstanding the Examiner’s erroneous claim construction, we agree
with the Examiner that Blandy’s disclosure of an interface that dynamically
switches between an execution mode and a debug mode and vice versa
teaches the disputed limitations. In other words, switching from the
execution mode to the debug mode indicates that a thread was being
executed at the time the switch occurred, thereby stopping the execution of
the thread in the execution mode to commence the debugging of the thread
in the debug mode. Further, even if Blandy’s disclosure of resuming the
debug operation indicates an initial switch from the debug mode to the
execution mode before resuming under the debug mode, we find nothing in
the claim that precludes such dynamic switching between the modes. We
are satisfied that Blandy’s disclosure of switching from the execution of a
thread to a debugging of the thread teaches the disputed limitations. It
follows that Appellants have not shown error in the Examiner’s rejection of
claim 1.
Claims 2, 4, 5, 7-10, and 14-17 not separately argued fall with claim 1
above. See 37 C.F.R. § 41.37(c)(1)(vii).

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DECISION
We affirm the Examiner’s rejections of claims 1, 2, 4, 5, 7-10, and 14-
17 as set forth above.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

ELD