Ex Parte Khodabandehlou et al

Patent Trials and Appeals Board

Mar 27, 2019

15273426 - (D) (P.T.A.B. Mar. 27, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
15/273,426 09/22/2016 Hamid Khodabandehlou
60909 7590 03/29/2019
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CA 95134-1709
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
CD06204C2 1795
EXAMINER
MERCADO, RAMON A
ART UNIT PAPER NUMBER
2132
NOTIFICATION DATE DELIVERY MODE
03/29/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patents@cypress.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte HAMID KHODABANDEHLOU and SYED BABAR RAZA
Appeal2018-006657
Application 15/273,426
Technology Center 2100
Before JAMES R. HUGHES, JOHN A. EV ANS, and JASON M. REPKO,
Administrative Patent Judges.
EV ANS, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 seek our review under 35 U.S.C. § 134(a) of the
Examiner's Final Rejection of Claims 1-5, which are all of the pending
claims. Appeal Br. 3. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE. 2
1 The Appeal Brief identifies Cypress Semiconductor Corporation, as the
real party in interest. Appeal Br. 1.
2 Rather than reiterate the arguments of Appellants and the Examiner, we
refer to the Appeal Brief (filed March 2, 2018, "Appeal Br."), the Reply
Appeal2018-006657
Application 15/273,426
STATEMENT OF THE CASE
The claims relate to a system comprising a memory controller coupled
to an external memory device. See Abstract.
INVENTION
An understanding of the invention can be derived from a reading of
Claim 1, the sole independent claim, which is reproduced below with some
formatting added:
1. A system comprising:
a memory controller; and
a memory device coupled to and external to the memory
controller, the memory device comprising:
a storage array having dual configurability to support
both synchronous and asynchronous modes of operation; and
a control logic including a control signal multiplexer
coupled to a chain of registers, wherein the control signal
multiplexer is configured to selectively forward a clock signal
or an asynchronous control signal to the chain of registers
depending on a selected mode of operation.
Brief (filed June 14, 2018, "Reply Br."), the Examiner's Answer (mailed
April 19, 2018, "Ans."), the Final Action (mailed October 4, 2017, "Final
Act."), and the Specification (filed September 22, 2016, "Spec.") for their
respective details.
2
Appeal2018-006657
Application 15/273,426
Manapat
Barth
References and Rejections3
US 6,327,175 Bl
US 7,085,906 B2
Dec. 4, 2001
Aug. 1, 2006
Pong P. Chu, RTL Hardware Design Using VHDL, John Wiley & Sons, Inc.,
Hoboken, NJ (April 2006).
Claims 1-5 stand rejected under 35 U.S.C. § I03(a) as being
unpatentable over Manapat, Barth, and Chu. Final Act. 4--9.
ANALYSIS
We have reviewed the rejections of Claims 1-5 in light of Appellants'
arguments that the Examiner erred. We consider Appellants' arguments
seriatim, as they are presented in the Appeal Brief, pages 3-7.
CLAIMS 1-5: OBVIOUSNESS OVERMANAPAT, BARTH,AND CHU.
Forwarding an asynchronous control signal
Claim 1 recites, inter alia, "wherein the control signal multiplexer is
configured to selectively forward a clock signal or an asynchronous control
signal." Appellants contend the prior art fails to teach a multiplexer
forwarding an asynchronous control signal. Appeal Br. 5.
3 The present application is being examined under the pre-AIA first to invent
provisions. Final Act. 2.
3
Appeal2018-006657
Application 15/273,426
The Examiner finds Manapat substantially teaches the limitations of
Claim 1 except that Manapat fails to teach "where the control signal
multiplexer is configured to selectively forward a clock signal or an
asynchronous control signal," as claimed. Final Act. 5. The Examiner finds
Barth "teaches a control logic including a control signal multiplexer
configured to selectively forward a clock signal or an asynchronous
control signal depending on a selected mode of operation." Final Act. 6.
The Examiner cites multiplexer 57 4 controlled by a control signal from
mode control circuit 566 over line 568; wherein when mode control circuit
566 applies a signal associated with the asynchronous transfer mode over
line 568, the signal on CAS line 506 passes from line 564 through
multiplexer 574 to the input of clock buffer 544; and wherein when mode
control circuit 566 applies a signal associated with the synchronous transfer
mode over line 568, the output of a delay lock loop (DLL) 572 whose input
is the external clock signal on line 512 passes through multiplexer 574 to the
input of clock buffer 544. Id. ( citing Barth, FIG. 5b; col. 7, 11. 24--45); see
Ans. 3--4.
Appellants contend that based on the express disclosure of Barth, "it is
clear that none of the line inputs 564, 512, and 568 is an asynchronous
control signal that can be forwarded to clock buffer 544 depending on the
mode of operation." Appeal Br. 5. (Citing Barth citing Barth, FIG. 5b; col.
7, 11. 24--45) (cited by the Examiner). We agree.
4
Appeal2018-006657
Application 15/273,426
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Barth, Figure 5b
Figure 5b shows Clock Generation Circuit 570 comprising
multiplexer "MUX" 574 having inputs 564 and 568 and input 576 from
Delay Lock Loop 572 which, in tum, has input 512 from an external clock
signal.
With reference to Figure 5b, Barth discloses a block diagram of clock
generation circuit 570. Barth, col. 5, 11. 2-5. Barth discloses Clock
generation circuit 570 includes multiplexer 574 with three inputs, lines 564,
576 and 512, and one output which feeds the input of clock buffer 544. Id.,
11. 26-9. Barth discloses multiplexer 574 is controlled by a control signal
5
Appeal2018-006657
Application 15/273,426
from mode control circuit 566 over line 568. Id., 11. 30-1. Barth discloses
three control modes. First, when mode control circuit 566 applies a signal
associated with the asynchronous transfer mode over line 568, a column
address strobe (CAS) signal passes from line 564 through multiplexer 574 to
the input of clock buffer 544. Id., 11. 32-5. Second, when mode control
circuit 566 applies a signal associated with the synchronous transfer mode
over line 568, the output of delay lock loop 572 whose input is the external
clock signal on line 512 passes through multiplexer 574 to the input of clock
buffer 544. Id., 11. 35--40. And third, when mode control circuit 566 applies
a signal associated with the slow synchronous transfer mode over line 568,
the external clock signal on line 512 passes through multiplexer 574 to the
input of clock buffer 544. Id., 11. 40--44.
Thus, Barth discloses an asynchronous mode, wherein a column
address strobe (CAS) signal passes through multiplexer 574 to the input of
clock buffer 544. And Barth further discloses synchronous and slow
synchronous modes, wherein an external clock signal on line 512 passes
through multiplexer 574 to the input of clock buffer 544. We agree with
Appellants that contrary to the Examiner's finding, Barth fails to teach or
suggest an asynchronous control signal is forwarded to a clock buffer.
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Appeal2018-006657
Application 15/273,426
DECISI0N4
The rejection of Claims 1-5 under 35 U.S.C. § 103 is REVERSED.
REVERSED
4 Because we do not sustain the Examiner's rejection for the reasons
discussed herein, we need not address Appellants' further arguments. See
Beloit Corp. v. Valmet Oy, 742 F.2d 1421, 1423 (Fed. Cir. 1984) (finding an
administrative agency is at liberty to reach a decision based on "a single
dispositive issue").
7