Ex Parte Kerwin et al

Patent Trial and Appeal Board

Jan 6, 2017

13218345 (P.T.A.B. Jan. 6, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/218,345 08/25/2011 David B. Kerwin UTMC158.4 7732
25235 7590 01/10/2017
HOGAN LOVELLS US LLP - Colorado Springs
TWO NORTH CASCADE AVENUE
SUITE 1300
COLORADO SPRINGS, CO 80903
EXAMINER
SLUTSKER, JULIA
ART UNIT PAPER NUMBER
2891
NOTIFICATION DATE DELIVERY MODE
01/10/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patentcoloradospring @ hoganlo veils, com
HLU S Docke ting @ hoganlovells. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte DAVID B. KERWIN and JOSEPH BENEDETTO1
Appeal 2015-0070512
Application 13/218,345
Technology Center 2800
Before JAMES C. HOUSEL, N. WHITNEY WILSON, and
CHRISTOPHER C. KENNEDY, Administrative Patent Judges.
KENNEDY, Administrative Patent Judge.
DECISION ON APPEAL
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s
decision to reject claims 1—5, 11—20, 22—28, and 30. We have jurisdiction
under 35 U.S.C. § 6(b). We AFFIRM as to claims 1-5, 11-20, 22-26, 28,
and 30. We DISMISS the appeal as to claim 27.
1 According to the Appellants, the real party in interest is Aeroflex Colorado
Springs Inc. Br. 1.
2 Though not identified by the Appellants or the Examiner, this appeal is
related to Appeal No. 2015-007054, which concerns Application Serial No.
13/218,352.
Appeal 2015-007051
Application 13/218,345
BACKGROUND
The subject matter on appeal relates to wafer structures used for the
manufacture of electronic integrated circuits. E.g., Spec. 1:14—15; Claim 1.
Claim 1 is reproduced below from page 6 (Claims Appendix) of the Appeal
Brief:
1. A wafer structure comprising:
a first region from a device wafer having at least one major
surface, a thickness, and a conductivity profile of a first
conductivity type substantially parallel to said at least one major
surface;
a second region from a separate handle wafer having a thickness,
and a second conductivity profile of a second conductivity type
opposite to that of said first region, such that said second region
is in electrical contact with said first region opposite the major
surface of said first region;
a bond interface region formed between said first region and said
second region; and
impurity sites in said first region, such impurity sites being
substantially electrically inactive over a temperature range, and
wherein the conductivity profile of said first region transitions
abruptly to the conductivity profile of said second region within
the interface region.
REJECTIONS ON APPEAL
1. Claims 1—5, 11—14, 16, 22, 26, and 28 stand rejected under 35
U.S.C. § 103(a) as unpatentable over Nakagawa et al. (US 4,935,386, issued
June 19, 1990) in view of Kononchuk et al. (US 6,346,460 Bl, issued Feb.
12, 2002).
2. Claims 15, 17—20, and 28 stand rejected under 35 U.S.C. § 103(a)
as unpatentable over Nakagawa in view of Kononchuk, further in view of
Morris (US 2007/0141794 Al, published June 21, 2007).
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Application 13/218,345
3. Claims 23—25 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Nakagawa in view of Kononchuk, further in view of
Brewer et al. (US 2003/0140317 Al, published July 24, 2003).
4. Claim 27 stands rejected under 35 U.S.C. § 103(a) as unpatentable
over Nakagawa in view of Kononchuk, further in view of Williams et al.
(US 5,648,288, issued July 15, 1997). This rejection is a new ground of
rejection entered in the Examiner’s Answer. See Ans. 2.
ANALYSIS
As an initial matter, we address the new ground of rejection of claim
27. Section 41.39(b) of Title 37, Code of Federal Regulations, states that if
an Examiner’s Answer includes a new ground of rejection, “to avoid sua
sponte dismissal of the appeal as to the claims subject to the new ground of
rejection,” an appellant must either (1) “[rjequest that prosecution be
reopened” or (2) “[rjequest that the appeal be maintained by filing a reply
brief.” The Appellants failed to take any action in response to the new
ground of rejection of claim 27 as obvious over Nakagawa, Kononchuk, and
Williams. Accordingly, we must dismiss the appeal as to claim 27, which is
the only claim that is subject to the new ground of rejection. See 37 C.F.R.
§ 41.39(b).
Turning to the remaining claims on appeal, after review of the cited
evidence in the appeal record and the opposing positions of the Appellants
and the Examiner, we determine that the Appellants have not identified
reversible error in the Examiner’s rejections. Accordingly, we affirm the
rejections for reasons set forth below, in the Final Action, and in the
Examiner’s Answer. See generally Final Act. 2—8; Ans. 2-4.
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Appeal 2015-007051
Application 13/218,345
The Appellants present arguments only with respect to claim 1. We
limit our discussion to that claim, and claims 2—5, 11—20, 22—26, 28, and 30
will stand or fall with claim 1.
The Examiner finds, and the Appellants do not dispute, that
Nakagawa teaches each element of claim 1 except the claimed impurity sites
in the first region. Final Act. 2—3. The Examiner finds that Kononchuk
discloses impurity sites in the device region of a wafer. Id. at 3. The
Examiner concludes that it would have been obvious “to modify Nakagawa
with Kononchuk to have impurity sites of said first region, such impurity
sites being substantially electrically inactive over a temperature range for the
purpose of protection against CMOS latch up.” Id.
The Appellants argue that Kononchuk teaches a device having only a
single wafer—a handle wafer rather than a device wafer. Br. 3^4. The
Appellants argue, therefore, that Kononchuk does not teach impurity sites in
a device wafer, as recited by claim 1. Id.
Largely for reasons stated by the Examiner, see Ans. 2—4, we do not
find that argument to be persuasive. As an initial matter, we note that the
Examiner’s rejection relies on both Kononchuk and Nakagawa, not on
Kononchuk alone. The Appellants do not dispute the Examiner’s finding
that Nakagawa teaches a wafer structure comprising both a handle wafer and
a device wafer. See Final Act. 2. Nor do the Appellants dispute the
Examiner’s finding that Kononchuk teaches that the addition of impurity
sites protects against CMOS latch up. See id. at 3. Regardless of whether
Kononchuk’s wafer is a handle wafer or a device wafer, the Appellants’
argument fails to persuasively address the Examiner’s determination that a
person of ordinary skill in the art would have been motivated to add impurity
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Application 13/218,345
sites to the device wafer portion of Nakagawa’s wafer structure with the
expectation that the impurity sites would protect against CMOS latch up.
See In re Keller, 642 F.2d 413, 426 (CCPA 1981) (“[0]ne cannot show non­
obviousness by attacking references individually where, as here, the
rejections are based on combinations of references.”).
In addition, in the Answer the Examiner explains that a person of
ordinary skill in the art would, in fact, have considered Kononchuk’s wafer
10 to be a device wafer comprising portions 12 and 18. See Kononchuk Fig.
1; Ans. 3^4. For example, the Examiner explains that, because CMOS
circuitry is formed in layer 18, which is part of wafer 10, wafer 10 is a
device wafer because “devices are formed therein.” Ans. 3^4; Kononchuk at
3:20. The Examiner also explains that certain similarities between
Kononchuk’s wafer and Nakagawa’s device layer, such as doping, indicate
that Kononchuk’s wafer “corresponds to the device wafer . . . of Nakagawa.”
Ans. 3^4. The Appellants do not file a Reply Brief to contest the
Examiner’s findings on those points, which are supported by the record.
Accordingly, we have no persuasive basis to reject those findings.
To the extent that the Appellants argue that Kononchuk’s impurity
sites are formed before layer 18 is deposited on layer 12, see Br. 4, the
Appellants do not persuasively explain why that would exclude the structure
of Nakagawa as modified by Kononchuk from the scope of claim 1. Claim 1
is directed to a wafer structure; it is not directed to a method of forming a
wafer structure.
On the record before us, having carefully considered the Appellants’
arguments, we determine that a preponderance of the evidence supports the
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Application 13/218,345
Examiner’s findings and conclusions. We affirm the Examiner’s rejection of
claim 1.
CONCLUSION
The appeal of claim 27 is DISMISSED for failure to respond to the
new ground of rejection in the Examiner’s Answer. See 37 C.F.R.
§ 41.39(b).
The Examiner’s rejections of claims 1—5, 11—20, 22—26, 28, and 30
are AFFIRMED.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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