Ex Parte Kershaw

Board of Patent Appeals and Interferences

Mar 30, 2009

10461880 (B.P.A.I. Mar. 30, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte DANIEL KERSHAW
____________________

Appeal 2009-0783
Application 10/461,8801
Technology Center 2100
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Decided:2 March 31, 2009
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Before: HOWARD B. BLANKENSHIP, JAY P. LUCAS, and
THU A. DANG, Administrative Patent Judges.

LUCAS, Administrative Patent Judge.

DECISION ON APPEAL

1 Application filed June 16, 2003. The real party in interest is ARM
Limited.

2 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 CFR § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Data (electronic delivery).
.
Appeal 2009-0783
Application 10/461,880

STATEMENT OF THE CASE
Appellant appeals from a final rejection of claims 1 to 9, 11 to 25, and
27 to 32 under authority of 35 U.S.C. § 134. The Board of Patent Appeals
and Interferences (BPAI) has jurisdiction under 35 U.S.C. § 6(b). An Oral
Hearing was held on March 18, 2009 at the USPTO.
Appellant’s invention relates to electronic computer processors
processing single instruction multiple data (SIMD) data processing systems
in which the calculation results are stored with the higher order results and
the lower order results in segregable portions. In the words of the Appellant:
Viewed from one aspect the present invention provides
apparatus for performing a data processing operation in response to a
data processing instruction, said apparatus comprising:

processing logic being responsive to said data processing
instruction to generate from a plurality of independent data values
stored within one or more input stores a respective plurality of result
data values.
(Spec., p. 3)

Claim 1 is exemplary:
1. Apparatus for performing a data processing operation in
response to a data processing instruction, said apparatus comprising:

processing logic, responsive to said data processing instruction,
for generating from a plurality of independent data values stored
within one or more input stores, a respective plurality of result data
values; and

a result partitioner, responsive to said data processing
instruction, for storing a high order bit portion of each result data
value within a high order result store and a low order bit portion of
each result data value within a low order result store.
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Appeal 2009-0783
Application 10/461,880

The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Kim US 6,564,238 B1 May 13, 2003
REJECTION
The Examiner rejects the claims as follows:

R1: Claims 1 to 9, 11 to 25, and 27 to 32 stand rejected under 35 U.S.C.
§ 102(e) for being anticipated by Kim.
Claims 33, 34 stand allowed by the Examiner. Claims 10 and 26 have
been indicated as containing allowable subject matter. (Br: 2, middle).
Appellant contends that the claimed subject matter is not anticipated
by Kim for failure of the reference to teach or suggest a key claim limitation.
The Examiner contends that each of the claims is properly rejected.
Rather than repeat the arguments of Appellant or the Examiner, we
make reference to the Briefs and the Answer for their respective details.
Only those arguments actually made by Appellant have been considered in
this opinion. Arguments which Appellants could have made but chose not to
make in the Briefs have not been considered and are deemed to be waived.
We affirm the rejection.

ISSUE
The issue is whether Appellants have shown that the Examiner erred
in rejecting the claims under 35 U.S.C. § 102(e). The issue turns on whether
the Kim reference teaches the plurality of result data values, with the storage
of the high order bit portions and low order bit portions as claimed.
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Application 10/461,880

FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence.
1. Appellants have invented an apparatus and method for partitioning the
results of numeric operations on stored data values into high order and
low order values, so that when only the approximate result is needed the
user can use just the high order values, and when full precision is needed
in the result both values are available. (Spec, p. 3, l. 12 – 23).
2. The reference Kim teaches storing the result of multiplying two stored
values into a temporary register 128 which is partitioned into high and
low order values. (Col. 8, l. 44 – 68). (Fig. 5).

PRINCIPLES OF LAW
“In reviewing the [E]xaminer’s decision on appeal, the Board must
necessarily weigh all of the evidence and argument.” In re Oetiker, 977
F.2d 1443, 1445 (Fed. Cir. 1992).
In rejecting claims under 35 U.S.C. § 102, “[a] single prior art
reference that discloses, either expressly or inherently, each limitation of a
claim invalidates that claim by anticipation.” Perricone v. Medicis Pharm.
Corp., 432 F.3d 1368, 1375-76 (Fed. Cir. 2005) (citation omitted).
“Anticipation of a patent claim requires a finding that the claim at
issue ‘reads on’ a prior art reference.” Atlas Powder Co. v. IRECO, Inc.,
190 F.3d 1342, 1346 (Fed Cir. 1999) (“In other words, if granting patent
protection on the disputed claim would allow the patentee to exclude the
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Application 10/461,880

public from practicing the prior art, then that claim is anticipated, regardless
of whether it also covers subject matter not in the prior art.”) (internal
citations omitted).
This court has held in a number of decisions that a United States
patent speaks for all it discloses as of its filing date, even when used in
combination with other references. In re Zenitz, 333 F.2d 924, 926 (CCPA,
1964) (internal citations omitted).
Our reviewing court states in In re Zletz, 893 F.2d 319, 321 (Fed. Cir.
1989) that “claims must be interpreted as broadly as their terms reasonably
allow.”
However, although elements must be arranged as required by the
claim, “this is not an ipsissimis verbis test, i.e., identity of terminology is not
required” In re Bond, 910 F.2d 831, 832 (Fed. Cir. 1990).

ANALYSIS
From our review of the administrative record, we find that the
Examiner has presented a prima facie case for the rejections of Appellant’s
claims under 35 U.S.C. § 102(e). The prima facie case is presented on page
3 of the Examiner’s Answer. In opposition, Appellant presents a number of
arguments.

Arguments with respect to the rejection
of claims 1 to 9, 11 to 25, and 27 to 32
under 35 U.S.C. § 102 [R1]
Appellant contends that the Examiner erred in rejecting the claims of
R1 as “the Examiner has not identified how or where Kim teaches SIMD
generally or the generation from a ‘plurality of independent data values,’ in
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Application 10/461,880

response to ‘a data processing instruction,’ the claimed ‘respective plurality
of result data values.’” (Brief 8: middle).
The Examiner has defended the rejection (Answer: 4) with a number
of arguments. The contention of whether the claim recites SIMD
processing, as asserted by the Appellant and denied by the Examiner, we
find to be a side issue. The term SIMD does not appear in the claim, and
only the terms of the claim are examined under an anticipation analysis.
(See In re Zenitz, cited above).
The claim requires that in response to “a data processing instruction”
processing logic generates from a plurality of stored data values a
“respective plurality of result data values.” First, we note that the claim does
not require that there be only a single instruction effecting the entire result –
the term “single” is not in the claim. (Brief 9: top). Thus if, for example,
there were a series of instructions needed to create the result, the execution
of the last of those instruction of the series would commence the operation
and start the generating of the results that anticipate the claim. Further, as
noted by the Examiner (Answer 4: middle), the claim does not require that
the plurality of result data values be generated in a single pass. Thus, as
applied to the Kim reference, instructions to multiply are sent by processor
12 or the equivalent to the processing logic in multiply and accumulate unit
(MAC) 64 of Fig. 5. (Col. 5, l. 40). The Examiner reasons that even were
the result data value sent to register 128 to be considered a single value, the
processing logic will produce a plurality of those result data values when a
plurality of input value sets are sent from input stores 106 and 108 and
serially multiplied. (Answer 4: option (1)). Thus, the processing logic
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Application 10/461,880

produces a respective plurality of result data values from the plurality of
independent data values, as recited in the claim. Giving the claims a broad
but fair reading, as above, (see In re Zletz, cited above.), we decline to find
error in the Examiner’s reasoning.
The Examiner further reasons that the “48-bit product of the multiplier
126 [which] is stored in the temporary register 128” (Col. 8, l. 52) could be
considered a plurality of data values since the 48 bit result is divided into the
least significant 24 bits stored in MULPL and the most significant 24 bits
stored in MULPH of register 128. (Answer 4: option (2)). This argument is
less persuasive in view of the next issue raised by Appellant.
Appellant argues that the Examiner fails to identify where Kim
teaches the claimed “results partitioner.” (Brief 9: middle). The Examiner
has read the partitioner on the temporary register 128. (Answer 3: bottom).
We find this to be a fair reading, as the result of the multiplication is stored
so as to place the high and low order bit portions in separately identified
stores MULPH and MULPL. Appellant argues that the Kim disclosure does
not handle a plurality of result data values. (Reply 7: top). We find this
unpersuasive, as a succession of multiplication results are sequentially stored
in the register. We thus, find the Examiner’s reading of the reference to be
fair, and its application to the claim limitation apt.

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CONCLUSION OF LAW
Based on the findings of facts and analysis above, we conclude that
the Examiner did not err in rejecting claims 1 to 9, 11 to 25 and 27 to 32.

DECISION
The Examiner's rejection of claims 1 to 9, 11 to 25, and 27 to 32 is
Affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

pgc

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