Ex Parte Karthikesan

Patent Trial and Appeal Board

Sep 6, 2016

13026447 (P.T.A.B. Sep. 6, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/026,447 02/14/2011 Nikanth Karthikesan
45838 7590 09/08/2016
SCHWEGMAN LUNDBERG & WOESSNER/NOVELL
POBOX2938
MINNEAPOLIS, MN 55402
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
1565.371US1 4914
EXAMINER
RUIZ, ARACELIS
ART UNIT PAPER NUMBER
2139
NOTIFICATION DATE DELIVERY MODE
09/08/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte NIKANTH KAR THIKESAN
Appeal2014-001198
Application 13/026,447
Technology Center 2100
Before ROBERT E. NAPPI, THU A. DANG, and DENISE M. POTHIER,
Administrative Patent Judges.
POTHIER, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner's
rejection of claims 1-20. See App. Br. 1. 1 We have jurisdiction under 35
U.S.C. § 6(b). We affirm.
Invention
Appellant's invention relates to "a method for managing local
memory in a multiprocessor system." Spec. i-fi-1 7, 46.
1 Throughout this opinion, we refer to the Final Action mailed November 23,
2012, Appeal Brief (App. Br.) filed April 22, 2013, the Examiner's Answer
(Ans.) mailed August 26, 2013, and the Reply Brief (Reply Br.) filed
October 28, 2013.
Appeal2014-001198
Application 13/026,447
Claim 1 is reproduced below with emphasis:
1. A method implemented in a non-transitory machine-readable
storage medium and processed by one or more processors configured
to perform the method, comprising:
detecting that a local memory for a first processor of a
multiprocessor system has reached a threshold capacity level;
identifying a second memory local to a second processor of the
multiprocessor system with excess capacity; and
offloading data from the local memory of the first processor to the
second memory local to the second processor to increase capacity of
the local memory and decrease capacity of the second memory,
wherein the local memory and the second memory are volatile
memories.
The Examiner relies on the following as evidence of unpatentability:
Kobayashi
Keeler
Dixon
Yagi
Ogawa
Kawaguchi
us 6,101,576
US 2005/0066121 Al
US 2006/0112252 Al
US 2007 /0186757 Al
US 2008/0052331 Al
US 2008/0184000 Al
The Rejections
Aug. 8,2000
Mar. 24, 2005
May 25, 2006
Aug. 16, 2007
Feb.28,2008
July 31, 2008
Claims 1, 4, 6-8, 11, 14, and 16-18 are rejected under 35 U.S.C.
§ 103(a) as unpatentable over Kawaguchi and Yagi. Ans. 5-11.
Claim 2 is rejected under 35 U.S.C. § 103(a) as unpatentable over
Kawaguchi, Yagi, and Dixon. Ans. 12.
Claims 3, 19, and 20 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Kawaguchi, Yagi, and Ogawa. Ans. 12-14.
Claims 5, 9, 12, 13, and 15 are rejected under 35 U.S.C. § 103(a) as
unpatentable over Kawaguchi, Yagi, and Keeler. Ans. 14--1 7.
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Application 13/026,447
Claim 10 is rejected under 35 U.S.C. § 103(a) as unpatentable over
Kawaguchi, Yagi, and Kobayashi. Ans. 17-18.
OBVIOUSNESS REJECTION OVER KAWAGUCHI AND YAGI
For independent claim 1, Appellant presents two central arguments.
First, Appellant asserts that Kawaguchi and Yagi fail to teach expanding
memory across multiple processors. App. Br. 7-9. Second, Appellant
contends that Kawaguchi and Yagi are not combinable. App. Br. 7, 9-11.
Appellant does not separately argue claims 4, 6-8, 11, 14, and 16-18.
See App. Br. 7-11. As such, we group claims 1, 4, 6-8, 11, 14, and 16-18
and treat claim 1 as representative. 37 C.F.R. § 41.37(c)(l)(iv).
ISSUE
Under 35 U.S.C. § 103, has the Examiner erred in rejecting claim 1 by
finding that Kawaguchi and Yagi teach and suggest "offloading data from
the local memory of the first processor to the second memory local to the
second processor to increase capacity of the local memory and decrease
capacity of the second memory"?
ANALYSIS
Based on the record before us, we find no error in the Examiner's
rejection of independent claim 1.
First, Appellant argues that Yagi teaches an apparatus having "a
single processing device." App. Br. 7-8. We are not persuaded. The
Examiner relies on Kawaguchi to teach the recited first and second
processors. Ans. 5---6, 18-19 (citing Kawaguchi i-fi-f 156-57, claim 20).
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Application 13/026,447
Claim 20 and Figure 1, in particular, describe and show an embodiment
having a first (e.g., 11111) and a second processor (e.g., 11211), each having
a memory connected to its processor respectively. Kawaguchi, ,-r 156-57,
page 20. As such, Kawaguchi teaches more than a single processor.
Appellant further asserts that "[t]here is no indication anywhere in
Yagi that multiple processors share memory or that memory for one
processor is decreased while memory of another processor is expanded."
App. Br. 8. Notably, claim 1 does not recite "expanded" or "shared"
memory or "memory expansion" (App. Br. 8), but rather "offloading data ..
. to increase capacity of the local memory and decrease capacity of the
second memory." App. Br. 13, Claims App'x. Similarly, the word
"expand" or derivatives of "expand" are not found in independent claims 11
and 18.
Regardless, this argument is unavailing, for this assertion attacks Yagi
individually without considering the relied-upon teachings in Kawaguchi in
combination with Yagi. See In re Merck & Co., Inc., 800 F.2d 1091, 1097
(Fed. Cir. 1986). Claim 20 of Kawaguchi includes one processor (e.g., a
first processor) judging whether the capacity of a free storage region in the
first storage module is exhausted. Kawaguchi, claim 20. If exhausted,
Kawaguchi teaches another processor (e.g., the second processor) receiving
the data from the first storage module and storing the data in a storage region
of the second data storage medium, which frees the storage region of the
first data storage medium (e.g., offloading data from the local memory of the
first processor to the second memory local to the second processor). Id.; see
also Kawaguchi i-fi-1156-57. At the cited portions, Kawaguchi discloses
migrating data from a storage module (e.g., storage module 11100) local to a
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Application 13/026,447
processor to another storage module local to another processor in order to
increase free capacity of a pool. See Kawaguchi i-fi-f 156-57.
The rejection additionally proposes to modify Kawaguchi to include
the teachings of Yagi. Ans. 5---6, 20. Specifically, Yagi teaches offloading
data from one memory unit of a processor to another memory unit, the
memory units being volatile memories. See Yagi i-fi-1 54, 56, Fig. 1, cited in
Ans. 5---6, 20. As explained in more detail below, when combined with
Kawaguchi, the proposed rejection modifies Kawaguchi's method to include
Yagi's technique so as to free the processor's memory by transferring data to
other volatile memory units. Ans. 6, 20; Adv. Act. 2.2 The resulting
combination suggests offloading data in the memory units of a processor to
memory units of another processor in order to free memory and increase
available memory space. Ans. 6, 20; Adv. Act. 2 (indicating the similarities
between the references).
Appellant next argues that the memory in Kawaguchi is non-volatile
and not "volatile" as recited, and the Examiner does not appreciate this
distinction. App. Br. 8. However, the Examiner states in the rejection that
Kawaguchi does not teach volatile memory, turning to Yagi in combination
with Kawaguchi for this teaching. Ans. 6, 19 (citing Yagi i-fi-1 54, 56). Thus,
the assertion by Appellant that "the references ... in combination with one
another do not show or suggest ... the memories are volatile" (App. Br. 9)
fails to consider the teachings of Kawaguchi and Yagi collectively, attacking
the references individually. See Merck, 800 F .2d at 1097.
Appellant even further asserts that Kawaguchi and Yagi are not
combinable. App. Br. 9-11; Reply Br. 2-3. Appellant contends that
2 The Advisory Action was mailed February 7, 2013.
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Application 13/026,447
Kawaguchi deals with storage expansion not memory expansion and that
there is no suggestion to expand memory in Kawaguchi. App. Br. 8-9;
Reply Br. 2-3. We noted above that claim 1 does not recite memory
expansion but rather offloading data from memory of a first processor to
memory local to another processor. App. Br. 13, Claims App'x. Yagi
provides such a teaching to offload data from one memory unit to another
memory unit. Yagi i-fi-1 54, 56.
Granted and as argued by Appellant (App. Br. 7-8, 10), Yagi teaches
offloading data within a system having a single processor. Yagi i1 52, Fig. 1.
But, the rejection relies on what Kawaguchi and Yagi collectively teach or
suggest. Kawaguchi teaches offloading data from memory associated with a
first processor to memory associated with a second processor. Kawaguchi
i-fi-f 156-57, claim 20, Fig. 1. Yagi teaches offloading data between
memories that are volatile. Yagi i-fi-1 54, 56. When combined, the teachings
yield no more than one skilled in the art would have expected - offloading
data from a local memory of a first processor to a memory local to a second
processor, the memories being volatile, to free memory storage and increase
available memory space. Ans. 6, 20; Adv. Act. 2.
Appellant further asserts that combining Yagi's teaching of memory
expansion with Kawaguchi would render Kawaguchi' s "storage expansion
approach" unsatisfactory for its intended purpose and change its core
principle. App. Br. 9-10. Specifically, Appellant states that Kawaguchi
relies on indexing memory to expand storage and "[ t ]here is no hint of a
suggestion in Kawaguchi that memory is being expanded[,] only
non-volatile storage." App. Br. 9. In Appellant's view, any modification to
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Kawaguchi' s storage system would render Kawaguchi' s technique useless
and further defies "common sense." App. Br. 10.
Yet, the rejection does not propose modifying Kawaguchi's indexing
system of Kawaguchi. Ans. 5-6, 20, Advisory Act. 2. Thus, Kawaguchi's
system, even when modified, would still include moving data in storage
between storage modules. See id. Instead, the rejection proposes modifying
Kawaguchi' s method to include Yagi's technique so as to free the
processor's memory, which can be volatile memory, by transferring data to
other volatile memory units. Id. As mentioned previously, Yagi teaches
moving the data to memory units of the same processor. Yagi i-fi-1 54, 56,
Fig. 1. However, combining Yagi's teaching off moving data in processor's
memory to different memory units (Yagi i-fi-1 54, 56, Fig. 1) with
Kawaguchi' s teachings of offloading data to memory units associated with
other processors (Kawaguchi i-fi-f 156-57, claim 20, Fig. 1) further suggest to
an ordinarily skilled artisan offloading data from a memory unit of a first
processor to a memory unit of another processor. Thus, when combined, the
references at least suggest to one skilled in the art offloading data in volatile
memory of a first processor to volatile memory local to a second processor
as recited.
Based on the above discussion, we disagree that Yagi does not relate
to "memory expansion" or offloading data as recited. App. Br. 9. That is,
Yagi teaches offloading data to a second data memory unit (e.g., 15) when
the data in one memory unit (e.g., 14) exceeds its capacity. Yagi i154,
Fig. 1. Additionally, we disagree that "Yagi is asserted as being used for
teaching non-volatile expansion." Reply Br 2. Rather, Yagi is cited to teach
that volatile memory is known in the art and that it is further known to
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Application 13/026,447
otlload data between volatile memory units. See Yagi if 54, Fig. 1, cited in
Ans. 6, 20; Adv. Act. 2.
We thus are not persuaded that the combination would render
Kawaguchi unsatisfactory for its intended purpose or useless. App. Br.
9-10. Nor are we persuaded that one skilled in the art would "shy away"
from such a combination. App. Br. 9.
Lastly, in an attempt to demonstrate that Kawaguchi and Yagi are not
combinable, Appellant argues various differences between volatile memory
and non-volatile storage. App. Br. 8; Reply Br. 2. These include: storage is
easily accessible over a network whereas memory is typically accessible on
the same device, storage is usually addressed as blocks whereas memory is
addressed as pages, memory expansion conventionally requires additional
hardware, memory is specific to a processor, and memory communications
occur over a data bus not a network. Id. Yet, Appellant provide no
objective supporting evidence of these distinctions, amounting to mere
assertions by counsel. Id. Given the record, we are not persuaded.
For the foregoing reasons, Appellant has not persuaded us of error in
the rejection of (1) independent claim 1 and (2) claims 4, 6-8, 11, 14, and
16-18, not separately argued.
THE REMAINING REJECTIONS
Appellant does not dispute the remaining rejections of claims 2, 3, 5,
9, 10, 12, 13, 15, 19, and 2 0. We summarily sustain the remaining rejection.
See Hyatt v. Dudas, 551F.3d1307, 1314 (Fed. Cir. 2008) (explaining that
when appellant fails to contest a ground of rejection, the Board may affirm
the rejection without considering its substantive merits); see also 37 C.F.R.
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Appeal2014-001198
Application 13/026,447
§ 41.37(c)(l)(iv); Manual of Patent Examining Procedure (MPEP)
§ 1205.02, 9th ed. (Nov. 2015) ("If a ground of rejection stated by the
examiner is not addressed in the appellant's brief, appellant has waived any
challenge to that ground of rejection and the Board may summarily sustain
it.").
CONCLUSION
The Examiner did not err in rejecting claims 1-20 under 35 U.S.C.
§ 103.
DECISION
The Examiner's decision rejecting claims 1-20 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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