Ex Parte Kapur

Board of Patent Appeals and Interferences

Dec 16, 2009

10978183 (B.P.A.I. Dec. 16, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
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Ex parte MOHIT KAPUR
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Appeal 2009-000904
Application 10/978,183
Technology Center 2800
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Decided: December 16, 2009
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Before KENNETH W. HAIRSTON, JOHN A. JEFFERY, and
THOMAS S. HAHN, Administrative Patent Judges.

HAHN, Administrative Patent Judge.

DECISION ON APPEAL
Appellant invokes our review under 35 U.S.C. § 134(a) from the
Examiner’s final rejection of claims 1-21. We have jurisdiction under 35
U.S.C. § 6(b). We reverse.

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STATEMENT OF THE CASE
Appellant claims an apparatus and method invention for changing a
clock frequency that is derived from a master clock, and for switching
between generated multiple frequencies. Two phase clock signals that do
not transition at substantially the same time are generated from the master
clock signal. One of the two phase clock signals is divided to create the
multiple frequencies, and the other phase clock signal is used to switch
between the generated multiple frequencies.1 Claim 1, with disputed
limitations emphasized, is illustrative:
1. A method of switching a frequency associated with a master clock,
comprising the steps of:

generating two phase clocks from a master clock, wherein the two
phase clocks do not transition at substantially the same time;

using one of the two phase clocks to create multiple frequencies by
dividing the one phase clock; and

using the other phase clock to switch between the multiple frequencies
of the one phase clock.

The Examiner relies on the following prior art references to show
unpatentability:
Kojima US 6,437,624 B1 Aug. 20, 2002
Shimogama2 JP 2003-216268 A July 31, 2003

1 See generally Spec. 3:21 – 4:24; 9:26 – 10:15; Figs. 1, 2A, 2B, 3A, 3B, and
4.
2 An English translation of this Japanese reference was entered in the record
on Nov. 28, 2007, and it is that translation that is referred to and is cited for
this decision as opposed to the prior entered machine language translation.
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Rejection
The Examiner rejected claims 1-21 under 35 U.S.C. § 103(a) as
unpatentable over Shimogama and Kojima (Ans. 3-5).
Rather than repeat the arguments of Appellant or of the Examiner, we
refer to the Briefs and the Answer3 for their respective details. In this
decision, we have considered only those arguments actually made by
Appellant. Arguments that Appellant could have made but did not make in
the Briefs have not been considered and are deemed to be waived. See 37
C.F.R. § 41.37(c)(1)(vii).
Appellant’s Arguments
Appellant collectively argues claims 1, 3, 4, 10-12, 14, 15, and 19-21
with separate argument for independent claim 1 (App. Br. 5-7). The argued
group includes all appealed independent claims. Accordingly, for this group
we select claim 1 as representative. See 37 C.F.R. § 41.37 (c)(1)(vii).
Appellant, referencing claim 1, asserts, inter alia, that the Examiner
“fails to explain how the cited combination teaches using one of the two
phase clocks to create multiple frequencies . . ., and using the other phase
clock to switch between the multiple frequencies of the one phase clock”
(App. Br. 6).
For the remaining dependent claims 2, 5-9, 13, and 16-18, the
Appellant repeats by reference the arguments made for claim 1, and also
argues, with explanations, that each of these claims recites patentable subject

3 We refer throughout this opinion to (1) the Appeal Brief filed Aug. 20,
2007, (2) the Answer mailed Nov. 9, 2007, and (3) the Reply Brief filed Jan.
9, 2008.
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matter (App. Br. 7, 8). The arguments beyond those made for claim 1 need
not be reached because the rejection of base independent claims will not be
sustained.
ISSUE
Under § 103(a), has Appellant shown that the Examiner erred by
finding the combined references teach or suggest (1) using one of two
generated phase clock signals to create multiple frequencies, and (2) using
the other phase clock signal to switch between the generated multiple
frequencies, as recited in claim 1?

FINDINGS OF FACT
The record supports the following Findings of Fact (FF) by a
preponderance of the evidence:
Shimogama
1. Shimogama discloses a clock selection circuit and method “with
improved switching speed when switching from a division clock
being outputted to a clock selected using selection signals”
(Shimogama, ¶ [0001]).
2. Shimogama’s Figure 1 is a block diagram for a clock selection circuit,
and Figure 2 is a block diagram for a selection signal generation
output circuit for Figure 1 (Shimogama, ¶ [0036]; Figs. 1 and 2
(reproduced below for reference)).

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Reproduction of Shimogama’s Figure 1 Showing a Clock Selection Circuit
Block Diagram

Reproduction of Shimogama’s Figure 2 Showing a Selection Signal
Generation Circuit Block Diagram for Figure 1
3. Referring to Shimogama Figures 1 and 2, a clock selection circuit (see
Fig. 1) is disclosed that includes an output selection signal generation
circuit “g”, and that output circuit (see Fig. 2) includes a flip-flop 6
with an input basic clock CK1 signal and a clock selection signal SEL
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to latch a selector 7 in order to output “clock selection signals
OUTSEL” (Shimogama, ¶ [0042]; Figs. 1 and 2).
4. Shimogama discloses that the described circuit and method provides
“(1) a basic clock; (2) a division means used to generate multiple
division clocks synchronized with the basic clock; and (3) a clock
selection means used to select any clock from the aforementioned
basic clock and the aforementioned multiple division clocks and
output it” (Shimogama, ¶ [0022]).
Kojima
5. Kojima discloses an apparatus and method for digital storage devices
that combines data and clock generation paths for an edge-triggered
latch (Kojima, col. 1, ll. 19-22).
6. Kojima explains that using clock pulses as a control input for a latch
circuit provides a flip-flop function that is triggered every time a clock
pulse goes to a one or zero logic level (Kojima, col. 1, ll. 27-30).
7. Positive and negative edge-triggered D-latch circuit diagrams having a
clock and a pair of differential signal inputs to output a pair of
differential signals are respectively shown by Kojima in Figures 5A
and 5B (Kojima, col. 2, ll. 61-67; col. 3, ll. 21-23; col. 4, ll. 53-55;
Figs. 5A and 5B).
8. For the positive edge-triggered D-latch circuit shown in Figure 5A,
Kojima discloses a control node 514 that has a pulse width
corresponding to a delay imparted on the input clock signal by
inverters 140 and 141. No circuit element “140” is exhibited for the
negative edge-triggered D-latch circuit shown in Figure 5B (Kojima,
col. 5, ll. 8-10; Fig. 5A).
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PRINCIPLES OF LAW
It is incumbent upon the Examiner, if rejecting claims under 35
U.S.C. § 103, to establish a factual basis to support the legal conclusion of
obviousness. See In re Fine, 837 F.2d 1071, 1073-74 (Fed. Cir. 1988). The
factual determinations are set forth in Graham v. John Deere Co., 383 U.S.
1, 17 (1966) (These determinations are the: (1) scope and content of the
prior art, (2) differences between the prior art and the claims at issue, and (3)
level of ordinary skill in the art). Furthermore,
“there must be some articulated reasoning with
some rational underpinning to support the legal
conclusion of obviousness’ . . . . [H]owever, the
analysis need not seek out precise teachings
directed to the specific subject matter of the
challenged claim, for a court can take account of
the inferences and creative steps that a person of
ordinary skill in the art would employ.”

KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007) (quoting In re
Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006)).

ANALYSIS
Claims 1, 3, 4, 10-12, 14, 15, and 19-21
Based on the record, we are persuaded the Examiner erred in rejecting
representative claim 1.
Appellant asserts that the Examiner “fails to explain how the cited
combination teaches using one of . . . two phase clocks to create multiple
frequencies . . ., and using the other phase clock to switch between the
multiple frequencies of the one phase clock, as required by [claim 1] . . .”
(App. Br. 6). More specifically, Appellant contends that the Examiner
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“seems to simply conclude that, given [the base clock signal] CK1 of
Shimogama and the output of inverter 140 of Kojima, the claimed steps
would just occur . . .[, and] there is absolutely no suggestion that an output
signal in Kojima would be usable to switch between the clocks” (id.).
The portion from the Examiner’s findings and reasoning for the
reported obviousness rejection that is relevant to Appellant’s argument
states:
. . . Shimogama's figures 1 and 2 show a clock generation circuit
having [a] plurality of frequencies. Figure 2 fails to shows the detail
of the negative edge trigger flip-flop 6. However, Kojima et al. figure
5B shows a negative edge trigger flip-flop having improved clock-to-
output performance and greater efficiency. Therefore, it would have
been obvious to one having ordinary skill in the art to use Kojima et
al.'s flip flop for Shimogama's flip-flop for the purpose of improving
the circuit performance. Thus, the modified Shimogama's figures 1
and 2 show: a method of switching a frequency associated with a
master clock, comprising the steps of: generating two phase clocks
(CK1 and output of Kojima's 140 in the modified Shimogama's flip
flop 6) from a master clock (CK1), wherein the two phase clocks do
not transition at substantially the same time . . .; using one (CK1) of
the two phase clocks to create multiple frequencies by dividing the
one phase clock (CK1, CK2, CK3, CK4); and using the other phase
clock to switch between the multiple frequencies of the one phase
clock.
(Ans. 3.)
In contradiction to these Examiner findings, we find that (1)
Shimogama discloses flip-flop 6 being included in a selection signal output
circuit (FF 3), but reasonable review of Shimogama does not identify flip-
flop 6 being used as a negative edge trigger flip-flop; and (2) Kojima’s
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circuit element 140 exclusively is disclosed as being an inverter included in
a positive edge-triggered D-latch circuit shown in Figure 5A (FF 8).
In response to Appellant’s Appeal Brief assertions, the Examiner
further explains that:
Shimogama's figure 2 shows that the output of flip flop 6 is the output
of circuit 3. Kojima et al.'s [sic] shows that the output of the flip flop
figure 5, which is used in Shimogama's flip flop 6, is generated based
on clock signal generated by the output of inverter 140. Thus, the
output of Kojima et al.'s inverter 140, which is the claimed other
phase clock, is used to control Shimogama's selection circuit 4, thus
meet the claimed limitation “using the other phase clock to switch
between the multiple frequencies of the one phase clock”
(Ans. 6, 7.) Appellant contests the assertions directed to Shimogama’s
selection circuit 4 by arguing that even if the Examiner were correct, “there
is absolutely no suggestion that the output signal in Kojima would be usable
to switch between the clocks generated in block 2 of Shimogama, which
require by the claimed step of using the other phase clock to switch between
the multiple frequencies of the one phase clock” (Reply Br. 4).
From Shimogama, we find flip-flop 6 outputting a signal to latch a
selector 7 based on an input basic clock signal CK1 and a clock selection
signal SEL (FF 3). In the case of Kojima, however, we find both the
positive and negative edge-triggered D-latch circuits being taught as
receiving a clock and a pair of differential signal inputs to output a pair of
differential output signals (FF 7).
With this record of reference teachings, the Examiner’s indicated
combination of Shimogama’s flip-flop 6 with Kojima teachings by
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unspecified modifications is problematic. Specifically, the Examiner’s
indicated combination does not rebut Appellant’s analysis because it lacks
evidence as to why and how a modified Shimogama flip-flop 6 circuit would
work as asserted by the Examiner.
For the foregoing reasons, Appellant has persuaded us of error in the
Examiner’s rejection of claim 1, and, therefore, we also are persuaded of
error in the rejection of claims 3, 4, 10-12, 14, 15, and 19-21 for similar
reasons.
Claims 2 and 13
Appellant asserts, inter alia, for claims 2 and 13 the arguments
addressed above, which are directed to base independent claims 1 and 12
(App. Br. 7). For reasons stated supra, Appellant persuaded us of error in
the Examiner’s rejection of the base independent claims, and we, therefore,
will also not sustain the rejection of dependent claims 2 and 13. Fine, 837
F.2d at 1076 (“Dependent claims are nonobvious under section 103 if the
independent claims from which they depend are nonobvious.”).
Claims 5 and 16
Appellant asserts, inter alia, for claims 5 and 16 the arguments
addressed above, which are directed to base independent claims 1 and 12
(App. Br. 7). For reasons stated supra, Appellant persuaded us of error in
the Examiner’s rejection of the base independent claims, and we, therefore,
will also not sustain the rejection of dependent claims 5 and 16. Fine, 837
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F.2d at 1076 (“Dependent claims are nonobvious under section 103 if the
independent claims from which they depend are nonobvious.”).
Claims 6 and 17
Appellant asserts, inter alia, for claims 6 and 17 the arguments
addressed above, which are directed to base independent claims 1 and 12
(App. Br. 8). For reasons stated supra, Appellant persuaded us of error in
the Examiner’s rejection of the base independent claims, and we, therefore,
will also not sustain the rejection of dependent claims 6 and 17. Fine, 837
F.2d at 1076 (“Dependent claims are nonobvious under section 103 if the
independent claims from which they depend are nonobvious.”).
Claims 7 and 18
Appellant asserts, inter alia, for claims 7 and 18 the arguments
addressed above, which are directed to base independent claims 1 and 12
(App. Br. 8). For reasons stated supra, Appellant persuaded us of error in
the Examiner’s rejection of the base independent claims, and we, therefore,
will also not sustain the rejection of dependent claims 7 and 18. Fine, 837
F2d at 1076 (“Dependent claims are nonobvious under section 103 if the
independent claims from which they depend are nonobvious.”).
Claims 8 and 9
Appellant asserts, inter alia, for claims 8 and 9 the arguments
addressed above, which are directed to base independent claim 1 (App. Br.
8). For reasons stated supra, Appellant persuaded us of error in the
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Examiner’s rejection of the base independent claims, and we, therefore, will
also not sustain the rejection of dependent claims 8 and 9. Fine, 837 F.2d at
1076 (“Dependent claims are nonobvious under section 103 if the
independent claims from which they depend are nonobvious.”).
CONCLUSION OF LAW
Appellant has shown that the Examiner erred in rejecting claims 1-21
under § 103.
ORDER
The Examiner’s decision rejecting claims 1-21 is reversed.

REVERSED

KIS

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