Ex Parte Kaplan et al

Patent Trial and Appeal Board

May 23, 2018

13861267 (P.T.A.B. May. 23, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/861,267 04/11/2013 David A. Kaplan
109712 7590 05/25/2018
Advanced Micro Devices, Inc.
c/o Davidson Sheehan LLP
6836 Austin Center Blvd.
Suite 320
Austin, TX 78731
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
1458-120349 9010
EXAMINER
MATIN, TASNIMA
ART UNIT PAPER NUMBER
2135
NOTIFICATION DATE DELIVERY MODE
05/25/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
docketing@ds-patent.com
AMD@DS-patent.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte DAVID A. KAPLAN and JEFF RUPLEY
Appeal2017-010967
Application 13/861,267
Technology Center 2100
Before JASON V. MORGAN, KARA L. SZPONDOWSKI, and
PHILLIP A. BENNETT, Administrative Patent Judges.
SZPONDOWSKI, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 appeal under 35 U.S.C. § 134(a) from the Examiner's
Final Rejection of claims 1, 3-9, and 11-20. Claims 2 and 10 have been
cancelled. We have jurisdiction under 35 U.S.C. § 6(b ).
We AFFIRM-IN-PART.
1 According to Appellants, the real party in interest is the assignee,
Advanced Micro Devices, Inc. App. Br. 1.
Appeal2017-010967
Application 13/861,267
STATEMENT OF THE CASE
Appellants' invention is directed to handling page crossing store
instructions. Spec. i-fi-f l, 6. Claims 1 and 9, reproduced below, are
representative of the claimed subject matter:
1. An apparatus, comprising:
a store queue comprising a plurality of entries configured
to store information associated with store instructions, wherein
a respective entry is configured to store a first portion of
information associated with a page crossing store instruction
that manipulates a processor to write first data to a first memory
page and second data to a second memory page;
at least one buffer configured to store a second portion of
information associated with the page crossing store instruction;
and
a picker configured to employ the at least one buffer as
an entry of the store queue for load operations and store
operations in response to the at least one buff er storing the
second portion of information,
wherein the information associated with a page crossing
store instruction comprises at least a portion of the data that is
to be stored.
9. A method, comprising:
storing a first portion of information associated with a
store instruction in a store queue, the store instruction being a
page crossing instruction that manipulates a processor to write
first data to a first memory page and second data to a second
memory page;
storing a second portion of information associated with
the store instruction in at least one buff er in response to the
store instruction being a page crossing store instruction; and
employing the at least one buffer as an entry of the store
queue for load operations and store operations in response to
the at least one buffer storing the second portion of information,
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Application 13/861,267
wherein the information associated with a store
instruction comprises at least a portion of the data that is to be
stored.
REJECTIONS 2
Claims 9-14 stand rejected under 35 U.S.C. § 102(a)(2) as being
anticipated by Kannan et al. (US 2013/0013862 Al; published Jan. 10,
2013) ("Kannan").
Claims 1, 3-7, 17, and 18 stand rejected under 35 U.S.C. § 103 as
being unpatentable over the combination of Kannan and Kopec et al. (US
2008/0189506 Al; published Aug. 7, 2008) ("Kopec").
Claims 15, 16, 19, and 20 stand rejected under 35 U.S.C. § 103 as
being unpatentable over the combination of Kannan and Tran et al. (US
5,887,152; issued Mar. 23, 1999) ("Tran").
ANALYSIS
Claim 9
Appellants argue Kannan does not disclose a "page crossing store
instruction," as recited in claim 9, because Kannan is directed to cache line
boundary-crossing load instructions, not page crossing store instructions.
App. Br. 6-7 (citing Spec. i-f 4). Appellants argue page crossing store
instructions are not supported in Kannan. App. Br. 7 (citing Kannan i-f 61 ).
We are not persuaded. Appellants' Specification states:
Store instructions may occasionally write information to
memory locations that are partly in a first memory page and
partly in a different (second) memory page. For example, some
2 The Examiner does not provide any findings with respect to claim 8, or
even identify under what statute claim 8 is rejected. Therefore, we
summarily reverse the Examiner's rejection of claim 8.
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Appeal2017-010967
Application 13/861,267
store instructions write portions of their data to two different
cache lines. This type of store instruction is called a misaligned
store instruction. A subset of misaligned store instructions write
to cache lines that are present in different memory pages, e.g ..
as defined by a memory management unit in the system. These
store instructions are called page crossing store instructions and
the portion of the information that is stored on the second
memory page may be referred to as misaligned information.
Spec. i-f 4 (emphasis added). In other words, according to Appellants, a page
crossing store instruction is a subset of misaligned store instructions.
Misaligned store instructions write portions of their data to two different
cache lines, while page crossing store instructions write portions of their
data to two different cache lines that are present in different memory pages.
Kannan generally describes "handling misaligned memory accesses
within a processor." Kannan Abstract. Appellants direct our attention to
paragraph 61 of Kannan, which recites "[a Jn alternate solution to allow
power reduction is to not support a single-issue slot for misaligned store
instructions that cross a page boundary ... " However, we disagree this
disclosure indicates Kannan does not support page crossing store
instructions. To the contrary, it indicates that it does support it; an alternate
solution is to not support it. Kannan also explicitly describes handling page
crossing store instructions, where, in describing the address array in the store
queue, states "[p ]age-crossing store instructions have two different page
numbers." Kannan i-f 56. Accordingly, we are not persuaded the Examiner
erred.
Appellants further argue Kannan does not disclose "storing a second
portion of information associated with the store instruction in at least one
buffer" and "employing the at least one buffer as an entry of the store queue
for load operations and store operations," as recited in claim 9. App. Br. 7-
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Application 13/861,267
9. Appellants argue "Kannan teaches that misaligned store instructions are
separated into two subsets of data that are simultaneously entered into a
single banked store queue," so "Kannan does not teach storing a first portion
of information associated with the store instruction in a store queue and a
second portion of information associated with the store instruction in at least
one buffer." Reply Br. 4--5; see also App. Br. 9.
We are not persuaded. The Examiner properly relies on Kannan's
separating the store instruction into two subsets and storing them in separate
banks. See Ans. 18-20. Kannan describes "[i]ifthe access is a store
instruction, the [load store unit] separates associated write data into two
subsets and simultaneously stores these subsets in separate cache lines in
separate banks of the store queue." Kannan Abstract; see also Kannan
i-fi-f 11, 52, 54, Figs. 3, 4, 9. Appellants have not sufficiently explained why
storing two subsets of write data in separate cache lines in separate banks
does not teach or suggest storing a first portion of information in a store
queue and a second portion of information associated with the store
instruction in at least one buffer. We note the claim language does not
require that the claimed buffer be separate from the store queue. We agree
with the Examiner that the separate banks may be treated as buffers. See,
e.g. Spec. i13 ("store instructions ... are buffered in a store queue").
Appellants further argue Kannan does not disclose "wherein the
information associated with a store instruction comprises at least a portion of
the data that is to be stored," as recited in claim 9. App. Br. 9-10; see also
Reply Br. 5. According to Appellants, "Kannan discuses storing information
associated with a page misaligned store instruction it is a page number that is
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Appeal2017-010967
Application 13/861,267
stored in a 'side structure' (Kannan, para [0056]), but a page number is not f!
portion of the data that is to be stored." Reply Br. 5.
We are not persuaded. Kannan's banked store queue includes an
address array that "may be used in combination with a data array." Kannan
i-f 52; Fig. 4; see also Fig. 3. The data array, which is not shown in Figure 4,
"holds the data of store instructions until these instructions commit."
Kannan i-f 5 3.
Accordingly, we are not persuaded the Examiner erred in rejecting
independent claim 9. For the same reasons, we are not persuaded the
Examiner erred in rejecting dependent claims 11-14, for which Appellants
provided substantially similar arguments. See App. Br. 10-11.
Claims 1 and 17
Appellants argue Kopec does not teach or suggest "a picker
configured to employ the buffer as an entry of the store queue for load
operations and store operations in response to the buffer storing at least a
portion of the data that is to be stored corresponding to a page crossing store
instruction," as recited in claim 1 and commensurately recited in claim 17.
App. Br. 12-13. Specifically, Appellants argue "the page crossing tracker
34 disclosed in Kopec stores address translation information, but does not
store at least a portion of the data that is to be stored as provided by claim 1.
Therefore, Kopec does not disclose a picker configured to employ the buffer
as an entry of the store queue in response to the buffer storing at least a
portion of the data that is to be stored." App. Br. 13.
Appellants' arguments are not persuasive because they address Kopec
individually, rather than the combination of Kopec and Kannan as relied on
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Appeal2017-010967
Application 13/861,267
by the Examiner. See Final Act. 8-9. The Examiner relies on Figures 1, 3,
and 4 and paragraphs 20 and 23 of Kopec to teach or suggest "a picker
configured to employ the at least one buffer," and on Kannan to teach or
suggest the rest of the limitation. Final Act. 8-9.
In the Specification, Appellants describe "CPU 105 includes a picker
145 that is used to pick instructions for the program 140 to be executed by
the CPU core 115." Spec. i-f 22. Kopec provides an instruction unit that
"provides centralized control of instruction flow to the execution units" and
the "execution units 14 execute instructions dispatched by the instruction
unit 12, including loading and storing information in the data cache 16."
Kopec i-f 20. Given this disclosure, we agree with the Examiner that Kopec
teaches or suggests a "picker configured to employ the at least one buffer."
Accordingly, we are not persuaded the Examiner erred in rejecting
independent claims 1 and 1 7. For the same reasons, we are not persuaded
the Examiner erred in rejecting dependent claims 3-7, 15-16, and 18-20, for
which Appellants provided substantially similar arguments. See App. Br.
13-14.
DECISION
The Examiner's rejection of claims 1, 3-7, 9, and 11-20 is affirmed.
The Examiner's rejection of claim 8 is reversed.
No time period for taking any subsequent action in connection with
this appeal maybe extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED-IN-PART
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