Ex Parte Kaplan

Patent Trials and Appeals Board

May 4, 2016

12626826 - (D) (P.T.A.B. May. 4, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/626,826 11/27/2009 David A. Kaplan
109712 7590 05/06/2016
Advanced Micro Devices, Inc,
c/o Davidson Sheehan LLP
700 Lavaca
Suite 1400-2323
Austin, TX 78701
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
l 458-TT6563 2897
EXAMINER
KIM, HONG CHONG
ART UNIT PAPER NUMBER
2138
NOTIFICATION DATE DELIVERY MODE
05/06/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
docketing@ds-patent.com
caitlin.taylor@ds-patent.com
beatrice. zepeda@ds-patent.com
PTOL-90A (Rev. 04/07)
UNITEn STATES PATENT ANn TRA.nEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte DAVID A. KAPLAN
Appeal2014-004711
Application 12/626,826
Technology Center 2100
Before CARL W. WHITEHEAD JR., KEVIN C. TROCK, and
ADAM J. PYONIN, Administrative Patent Judges.
PYONIN, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) from the
Examiner's maintained Final Rejection of claims 1, 6, 8-18, and 20. See
Advisory Action 2. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
STATEMENT OF THE CASE
Introduction
Appellant's disclosure is directed to "data processing devices, and
more particularly to data processing devices having a cache memory." Spec.
Appeal2014-004711
Application 12/626,826
if 1. Claims 1, 14, and 16 are independent. Claim 1 is reproduced below for
reference:
1. A method of data processing comprising:
initiating a data access request responsive to executing an
instruction obtained from a memory location; and
restricting access to a portion of a cache memory by the data
access request responsive to the memory location storing the
instruction.
References and Rejections1
Claims 1, 14, and 16 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Frame (US 5,638,532; June 10, 1997). Final Action 3.
Claims 6, 8-13, 17, 18, and 20 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Frame and Mohamed (US 5,966,734;
Oct. 12, 1999) or Liao (US 6,859,862 Bl; Feb. 22, 2005). Final Action 4;
Answer 2.
Claim 15 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Frame, Mohamed or Liao, and further in view of
Courtright (US 6,430,655 Bl; Aug. 6, 2002). Final Action 12.
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellant's
arguments that the Examiner has erred. We agree with the Examiner's
responses to the issues raised by Appellant in the Appeal Brief for the
reasons given in the Answer. We adopt the findings of fact made by the
1 The Examiner has withdrawn the rejection of claims 1-20 under 35
§ U.S.C. 112 (pre-AIA), first paragraph, and has indicated dependent claims
2-5, 7, and 19 would be allowable if rewritten in independent form. See
Answer 2.
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Appeal2014-004711
Application 12/626,826
Examiner in the Final Action, the Advisory Action, and Examiner's Answer
as our own, and we highlight the following issues raised in the Reply Brief
for completeness.
A. Independent Claims 1, 14, and 16
Appellant argues the Examiner erred in rejecting independent claim 1,
because:
In the example proffered by the Examiner's Answer, the BIOS
call is alleged to be the data access request and the system
management code instruction issuing the BIOS call is alleged to
be the instruction. In the cited example, only the instruction
itself is non-cacheable because it is in the DXXXXH address
space. Frame does not disclose whether the data location
targeted by a BIOS call would be cacheable or not. Even if it
assumed, arguendo, that the data targeted by the BIOS call is
non-cacheable, that determination would be based on the
memory location of the data, not on the memory location of the
instruction giving rise to the BIOS call.
Reply Brief 2 (emphasis added).
Appellant's arguments are unpersuasive for not being commensurate
with the scope of the claim limitations. Although the claims are interpreted
in light of the specification, "limitations are not to be read into the claims
from the specification." In re Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir.
1993). Here, Appellants refer to terms such as "based on," that are not
recited in claim 1. Rather, we agree with the Examiner that the "restricting
access to a portion of a cache memory by the data access request" limitation
of claim 1 broadly but reasonably encompasses the disabled caching of the
address space for the BIOS calls, as disclosed by Frame. See Answer 9
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Application 12/626,826
(citing Frame 5:50-60) see also Frame Fig. 2.2 Frame further discloses the
BIOS calls are responsive to the system management code stored in a
memory space; thus, we agree with the Examiner that Frame broadly but
reasonably discloses the recitation "responsive to the memory location
storing the instruction." See id. Appellant's arguments, in contrast, fail to
persuasively compare and contrast the particular claim limitations with the
Examiner's findings to show error therein.
Accordingly, we are not persuaded the Examiner erred in finding
Frame discloses all limitations recited in claim 1, and independent claims 14
and 16 which recite similar limitations. See Appeal Brief 5.
B. Dependent Claims 9, 10, 17, and 20
Appellant argues "[t]here is no mention in any of the cited art of
allowing access to the cache if the instruction initiating the data access
request is in a selected address range" as recited by claims 10 and 20,
because "Frame, Mohamed, and Liao only refer to determining whether the
data itself is in a cacheable or non-cacheable range when determining
cacheability, not to allowing access to the cache for a data access based on
the location of the instruction whose execution initiates the data access for
the data." Reply Brief 4. Appellant presents similar arguments for claims 9
and 1 7, and further contends none of the cited references teach that the
required address range is of a firmware memory. Id. at 3.
2 Separately, we note Frame explains certain restrictions on access are
because "[c]ode residing above the first Mbyte ... is restricted from using
far 'jump' instructions to access code outside of the segment in which it
resides" whereas code residing below the first Mbyte (including the BIOS) is
fully mapped and would be overlaid. Frame 4:27-52.
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Appeal2014-004711
Application 12/626,826
Appellant's arguments do not persuade us the Examiner erred in
finding the combinations of Frame with Mohammed or Liao teach or suggest
the disputed limitations. "The test for obviousness is not ... that the
claimed invention must be expressly suggested in any one or all of the
references. Rather, the test is what the combined teachings of the references
would have suggested to those of ordinary skill in the art." In re Keller, 642
F.2d 413, 425 (CCPA 1981) (internal citations omitted).
Here, we agree with the Examiner that Frame teaches restricting
access to portions of the cache memory responsive to the memory location
storing the instruction, as discussed above. Further, Appellant has not
provided persuasive evidence or reasoning to show the Examiner erred in
finding the combinations of Frame with Liao or Mohammed teach or suggest
the instruction obtained from a selected address range. See Answer 10
(citing Frame 9: 10-65; Mohamed 3: 1-15; Liao 4:26-43).
Regarding the additional limitations of claims 9 and 17, Appellant's
argument that "[t]here is no mention of firmware at all" in the cited
references (Reply Brief 3) does not persuade us that one of ordinary skill, in
view of the teachings of Frame and Mohamed or Liao, would not use a
selected address range of a firmware memory. See Answer 10; see also
Frame Fig. 2; Mohamed Fig. 2; Liao Abstract (describing a "locked cache");
KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007) ("a court can take
account of the inferences and creative steps that a person of ordinary skill in
the art would employ.")
Accordingly, we are not persuaded the Examiner erred in finding
claims 9, 10, 17, and 20 are obvious in view of the cited references.
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Application 12/626,826
CONCLUSION 3
We are not persuaded the Examiner erred in rejecting independent
claims 1, 14, and 16, and dependent claims 9, 10, 17, and 20. Appellant
advances no further arguments regarding the 35 U.S.C. § 103 rejections of
claims 6, 8, 11-13, 15, and 18, thus we also sustain these rejections for the
reasons discussed herein. See Appeal Brief 8-9, Reply Brief 2-3.
DECISION
The Examiner's rejections of claims 1, 6, 8-18, and 20 are affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
3 In the event of further prosecution, the Examiner is invited to consider
whether the "processor" recited in either of independent claims 14 and 16
should be interpreted as a non-structural term that invokes application of 35
U.S.C. § 112, sixth paragraph (pre-AIA). In such case, the Examiner should
further consider whether these claims should be subject to an enablement
rejection under 35 U.S.C. § 112, first paragraph for reciting a "single
means." See MPEP § 2164.08(a) (citing In re Hyatt, 708 F.2d 712, 714--715,
(CAFC 1983) (A single means claim which covered every conceivable
means for achieving the stated purpose was held nonenabling for the scope
of the claim because the specification disclosed at most only those means
known to the inventor.))
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