Ex Parte KANG

Patent Trial and Appeal Board

Dec 18, 2017

13725538 (P.T.A.B. Dec. 18, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/725,538 12/21/2012 Teckgyu KANG NVDA/SC-l 1-0232-USl 6829
102324 7590 12/20/2017
Arte.ois T aw Omim T T P/NVTDTA
EXAMINER
7710 Cherry Park Drive Suite T #104
Houston, TX 77095
HUYNH, ANDY
ART UNIT PAPER NUMBER
2818
NOTIFICATION DATE DELIVERY MODE
12/20/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
kcruz @ artegislaw.com
ALGdocketing @ artegislaw.com
rsmith @ artegislaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte TECKGYU KANG
Appeal 2017-003153
Application 13/725,53 81
Technology Center 2800
Before BEVERLY A. FRANKLIN, BRIAN D. RANGE, and
DEBRA L. DENNETT, Administrative Patent Judges.
RANGE, Administrative Patent Judge.
DECISION ON APPEAL
SUMMARY
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
decision rejecting claims 1—7, 9—13, and 21. We have jurisdiction under 35
U.S.C. § 6(b).
We REVERSE.
1 The Appellant is NVIDIA Corporation, and Appellant also identifies
NVIDIA Corporation as the real party in interest. Appeal Br. 3.
Appeal 2017-003153
Application 13/725,538
STATEMENT OF THE CASE2
Appellant describes the invention as relating to an integrated circuit
chip packaging using an interposer substrate with through-silicon vias.
Spec. 11. Appellant states that the invention seeks to reduce warpage of the
interposer board and reduce footprint. Id. at | 6. Claim 1, reproduced below
with emphasis added to certain key recitations, is illustrative of the claimed
subject matter:
1. A microelectronic package, comprising:
an interposer that is formed from a semiconductor
substrate and includes a plurality of through-silicon vias;
a semiconductor die coupled to a first surface of the
interposer;
a mold compound connected to an edge surface of the
interposer and configured to stiffen the microelectronic package;
and
a packaging substrate coupled to a second surface of the
interposer, wherein the first surface of the interposer is opposite
to the second surface of the interposer.
Appeal Br. 13 (Claims App’x).
REFERENCES
The Examiner relies upon the prior art below in rejecting the claims
on appeal:
Wuetal. US 2011/0291288 A1 Dec. 1,2011
(hereinafter “Wu”)
2 In this opinion, we refer to the Final Office Action dated July 9, 2015
(“Final Act.”), the Appeal Brief filed August 8, 2016 (“Appeal Br.”), the
Examiner’s Answer dated October 24, 2016 (“Ans.”), and the Reply Brief
filed December 27, 2016 (“Reply Br.”).
2
Appeal 2017-003153
Application 13/725,538
Jeng et al. US 2013/0087920 A1 Apr. 11, 2013
(hereinafter “Jeng”)
REJECTIONS
The Examiner maintains the following rejections on appeal:
Rejection 1. Claims 1, 2, 4, 6, 7, 9, 10, and 21 under 35 U.S.C. § 102
as anticipated by Wu. Final Act. 4.3
Rejection 2. Claim 3 under 35 U.S.C. § 103(a) as unpatentable over
Wu. Id. at 8.
Rejection 3. Claims 5 and 11—13 under 35 U.S.C. § 103(a) as
unpatentable over Wu in view of Jeng. Id.
ANALYSIS
The Examiner finds that Wu teaches a microelectronics package with
interposer 510 which includes vias 515, a semiconductor die 530 coupled to
a first side of the interposer, a mold compound 517 connected to the edge of
the interposer, and “a packaging substrate/interconnect structure 511”
coupled to the second surface of the interposer. Final Act. 4; see also Wu
Fig. 5.
Appellant’s arguments present a focused question on appeal: has the
Examiner established that the structure labeled as 511 in Figure 5 of Wu is a
“packaging substrate” as recited in Appellant’s claim 1?
3 The Final Office Action rejects other claims as well as part of these same
rejections, but Appellant subsequently cancelled these claims and does not
raise them on Appeal. See Appeal Br. 12 (summarizing errors argued on
appeal), 13—15 (indicating claims 8, 14—20, and 22 have been cancelled).
3
Appeal 2017-003153
Application 13/725,538
Appellant argues that while the “packaging substrate” may include
interconnects, not everything with interconnects is necessarily a packaging
substrate. Appeal Br. 10; see also Spec. 121. Appellant further argues that
the Specification explains that a packaging substrate as a “rigid and
thermally insulating substrate” that provides a package “with structural
rigidity.” Reply Br. 4 (quoting Spec. 121). Appellant further states that the
claimed packaging substrate is an organic substrate. Id. at 6 (referring to
“the claimed packaging substrate (i.e., an organic substrate)”); see also
Appeal Br. 10 (referring to “a packaging substrate (i.e., an organic
substrate”)). We also note that claim 1 makes a distinction between the
recited “interposer” and the recited “packaging substrate” which must be
“coupled to a second surface of the interposer.” Appeal Br. 13 (Claims
App’x).
Appellant correctly states that Wu describes structure 511 (i.e., the
structure that the Examiner maps to the recited “packaging substrate”) as
“interconnect structure 511.” Appeal Br. 9; see also Wu 24, 50. Figure 5
of Wu shows that interconnect structure 511 is part of interposer 510.
Appeal Br. 9—10; see also Wu 1 60 (referring to “interposers 210-510”).
Appellant also argues that Wu discourages the use of an organic substrate
(Appeal Br. 10—11) and that Wu teaches structures other than interconnect
structure 511 as serving the purpose of a packaging substrate (Reply Br. 5—
6).
The Examiner responds to Appellant’s arguments by stating that
“[t]he terms ‘packaging substrate’ and/or the ‘interposer’ are considered [] a
relatively] broad term.” Ans. 3. The Examiner further states that the issue
is “just labeling because a microelectronic package as recited in Claim 1 and
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Appeal 2017-003153
Application 13/725,538
Figure 5 of Wu is considered having a same/equivalent structure.” Id. In
the context of claim 1 and the Specification, however, there is a distinction
between the recited interposer and the recited packaging substrate. And, as
explained above, Wu indicates that interconnect structure 511 is part of
interposer 510 rather than being a packaging substrate. Given the evidence
before us as a whole, the Examiner has not adequately explained why Wu’s
teaching of an interconnect structure 511 discloses a “packaging substrate”
as recited by claim 1. See, e.g., In re Gleave, 560 F.3d 1331, 1334 (Fed. Cir.
2009) (explaining that an anticipatory reference “must disclose each and
every element of the claimed invention”).
Accordingly, we do not sustain the Examiner’s rejection of claim 1.
All other claims on appeal depend from claim 1, and the Examiner’s
explanation of, for example, the Jeng reference does not cure the error
addressed above. We therefore do not sustain the Examiner’s rejection of
claims 2—7, 9-13, and 21.
DECISION
For the above reasons, we reverse the Examiner’s rejections of
claims 1—7, 9-13, and 21.
REVERSED
5