Ex Parte Kahler et al

Patent Trial and Appeal Board

Feb 11, 2015

12368032 (P.T.A.B. Feb. 11, 2015)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte DAVID RAY KAHLER, ANJUL MATHUR, and
RICHARD ANTHONY RIPBERGER
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Appeal 2012-009283
Application 12/368,032
Technology Center 2400
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Before CARL W. WHITEHEAD JR., JEFFREY S. SMITH, and
CATHERINE SHIANG, Administrative Patent Judges.

SHIANG, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1–25. We have jurisdiction under 35 U.S.C. § 6(b). We
affirm.
In reaching the decision, we have considered only the arguments
Appellants actually raised. Arguments Appellants did not make are deemed
to be waived. See 37 C.F.R. § 41.37(c)(1)(vii) (2011).

STATEMENT OF THE CASE
The present invention relates to safeguarding computer data. See
generally Spec. 1. Claim 1 is exemplary:
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1. A method for safeguarding nonvolatile storage (NVS) data by a
processor in communication with a memory device following a power
loss event, comprising:
encrypting a first portion of the NVS data using a first buffer
module; and
subsequently transferring the first portion of the NVS data to at
least one shared storage device while simultaneously encrypting a
second portion of the NVS data using a second buffer module,
subsequently transferring the second portion of the NVS data to the at
least one shared storage device.

THE REJECTIONS
Claims 1–5, 7–14, 16–21, and 23–25 are rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Iida (US 2008/0189484 A1; Aug. 7,
2008), Smith (US 5,329,623; July 12, 1994), and Corrigan (US 5,179,662;
Jan. 12, 1993).
Claims 6, 15, and 22 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Iida, Smith, Corrigan, and Acton (US 2006/0212644 A1;
Sept. 21, 2006).

ISSUES
Under 35 U.S.C. § 103, has the Examiner erred by finding Iida, Smith,
and Corrigan collectively teaches:
encrypting a first portion of the NVS data using a first
buffer module; and
subsequently transferring the first portion of the NVS
data to at least one shared storage device while simultaneously
encrypting a second portion of the NVS data using a second
buffer module,
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as recited in claim 1?

ANALYSIS
On this record, we find the Examiner did not err in rejecting claim 1.
We disagree with Appellants’ arguments (App. Br. 9–13; Reply Br.
2–5), and agree with and adopt the Examiner’s findings and conclusions on
pages 4–7 and 12–14 of the Answer as our own. Therefore, we limit our
discussion to the following points for emphasis.
First, Appellants cite the Specification throughout their arguments.
For example, instead of citing a claim limitation, Appellants contend:
[T]he Corrigan teachings illustrate that if the first buffer is not
finished writing the by the time the second buffer is ready to be
written, the size of buffers are readjusted (See Corrigan
abstract). Yet, the claims of the present invention provides for
the saving a data in write cache in a short period of time by
using only two buffers of predetermined size, with each buffer
capable of reading/encrypting and writing to FHD [fire hose
dump] disk.

App. Br. 11 (Appellants repeat the same on App. Br. 13). In another
example, Appellants argue while Iida teaches writing to nonvolatile
memory, the invention relates to data saved on a FHD. See App. Br. 12. In
a third example, Appellants cite Specification examples, but claim 1 does
not recite many details from the Specification examples. See App. Br. 9–10;
Reply Br. 2–3.
We do not import limitations from the Specification into the disputed
claim terms. It is well established that during examination, claims are given
their broadest reasonable interpretation consistent with the specification, but
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without importing limitations from the specification. See In re Am. Acad. of
Sci. Tech Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004) (citations omitted);
SuperGuide Corp. v. DirecTV Enters., Inc., 358 F.3d 870, 875 (Fed. Cir.
2004). Appellants do not contend that the inventors have assigned special
meanings to the disputed claim terms. Instead, as discussed above,
Appellants cite examples from the Specification, and argue that cited
references do not teach those examples from the Specification. See App. Br.
9–12. In fact, Appellants do not map those Specification examples to the
claim. See App. Br. 9–12.
Second, Appellants assert while the invention requires
“simultaneously writing and encrypting portions of the NVS data to a
storage device in parallel,” the cited references do not teach using double
buffering to encrypt data prior to write it to the NVS storage device. See
App. Br. 9–10. Appellants argue Iida fails to teach encryption using a first
and second buffer, and Smith and Corrigan are silent about using a first and
second buffer to encrypt and write to a storage device. See App. Br. 10; see
also 3–5. Appellants contend the combination of Iida and Corrigan would
result in using double buffering for writing data. See App. Br. 10–11. Later,
Appellants assert the combination of Iida and Corrigan would result in using
double buffering for encrypting data, but provide no support for such
assertion. See Reply Br. 5.
Appellants fail to show reversible error. Appellants’ arguments that
Iida fails to teach encryption using a first and second buffer, and Smith and
Corrigan are silent about using a first and second buffer to encrypt and write
to a storage device, are unpersuasive. Because the Examiner relies on cited
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references collectively to teach the disputed claim limitations, Appellants
cannot establish nonobviousness by attacking the references individually.
See In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986).
Further, the Examiner provides comprehensive mappings to show the
cited references collectively teach “encrypting a first portion of the NVS
data using a first buffer module; and subsequently transferring the first
portion of the NVS data to at least one shared storage device while
simultaneously encrypting a second portion of the NVS data using a second
buffer module,” as recited in claim 1. See Ans. 4–7 and 12–14. The
Examiner correctly finds Iida teaches the claim element “nonvolatile storage
(NVS) data.” See Ans. 4–5 (citing Iida ¶ 47, Fig. 2). Based on that finding
and Iida’s Figure 7, the Examiner finds Iida teaches “encrypting . . . the
NVS data . . . ,” and “subsequently transferring the . . . NVS data to at least
one shared storage device.” See Ans. 5. As a result, Iida teaches the claim
element “encrypting,” and Corrigan does not need to teach that claim
element.
It is undisputed Corrigan teaches double buffering, which is well
known in the art. See Ans. 12–13; App. Br. 10. Further, the Examiner
correctly finds Corrigan teaches “[writing] a first portion of the . . . data . . .
using a first buffer module,” and “subsequently transferring the first portion
of the . . . data to at least one shared storage device while simultaneously
[writing] a second portion of the . . . data using a second buffer module,” as
recited in claim 1. See Ans. 13. Therefore, Iida and Corrigan collectively
teaches “encrypting a first portion of the NVS data using a first buffer
module; and subsequently transferring the first portion of the NVS data to at
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least one shared storage device while simultaneously encrypting a second
portion of the NVS data using a second buffer module,” as recited in claim
1. Using Corrigan’s well known double buffering technique in the Iida
method would have predictably used prior art elements according to their
established functions—an obvious improvement. See KSR Int’l Co. v.
Teleflex, Inc., 550 U.S. 398, 422 (2007).
Accordingly, we sustain the Examiner’s rejection of independent
claim 1, and claims 2–25 for similar reasons.

DECISION
The Examiner’s decision rejecting claims 1–25 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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