Ex Parte Kadosh

Board of Patent Appeals and Interferences

Oct 29, 2007

10752818 (B.P.A.I. Oct. 29, 2007)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte AVIRAN KADOSH
____________________

Appeal 2007-2569
Application 10/752,818
Technology Center 2800
____________________

Decided: October 29, 2007
____________________

Before: JOSEPH F. RUGGIERO, ROBERT E. NAPPI and
KEVIN F. TURNER, Administrative Patent Judges.

TURNER, Administrative Patent Judge.

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134 from a final rejection of
claims 1-3, 5, 6, 8-12, 14, 15, 17-24 and 28-33. Claims 4, 7, 13, 16, 25-27,
34 and 35 have been indicated by the Examiner as containing allowable
subject matter. We have jurisdiction under 35 U.S.C. § 6(b). We reverse the
Examiner’s rejections.

STATEMENT OF CASE
Appellant discloses a phase lock circuit that can be used to produce a
signal having a known phase relationship to a source clock at the output of
an indeterminate circuit element. (Specification 2, ¶ [0005]). The circuit
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Application 10/752,818

receives clock and phase lock signals and produces a phase lock pulse based
on those signals; the indeterminate circuit receives the phase lock pulse and
produces an output signal having a known phase relationship to the clock
signal.
The independent claim 1, which is deemed to be representative, reads
as follows:
1. A phase lock circuit, comprising:
an input configured to receive a phase lock signal;
a clock configured to generate a clock signal;
phase lock circuitry in communication with the input and the
clock, the phase lock circuitry configured to generate a phase
lock pulse based on the phase lock signal and the clock signal;
and
a phase indeterminate circuit element producing an output
signal having a first phase, the phase indeterminate circuit
element configured to receive the phase lock pulse and to
generate an adjusted output signal, having a second phase,
based on the phase lock pulse, the adjusted output signal having
a known phase relationship to the clock signal.

The Examiner rejected claims 1-3, 5, 6, 8, 10-12, 14, 15, 17, 19-24
and 28-33 under 35 U.S.C. § 102(b) as being anticipated by Pierschel. The
Examiner also rejected claims 9 and 18 under 35 U.S.C. § 103(a) as being
unpatentable over Pierschel.
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Pierschel US 6,593,782 B2 Jul. 15, 2003
Appellant contends that the Examiner erred in indicating that the
claimed subject matter would have been anticipated or obvious. More
specifically, Appellant has argued that numerous claim elements are neither
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taught nor suggested by Pierschel and that the rejections are improper. (Br.
11-15). The Examiner finds that all elements of the rejected claims can be
found in Pierschel when given their broadest reasonable interpretation.
(Answer 6-10).

ISSUE
Has Appellant shown that the Examiner has failed to establish that all
of the disputed elements of the rejected claims are taught or suggested by
Pierschel?

FINDINGS OF FACT
1. Appellant discloses a phase lock circuit that can be used to produce
a signal having a known phase relationship to a source clock at the output of
an indeterminate circuit element. (Specification 2, ¶ [0005])
2. The phase lock circuitry receives a clock signal and a phase lock
signal as inputs and generates a phase lock pulse. (Specification 8-10, ¶
[0025], [0026], [0028] & [0029]; Figs. 2A & 3A; elements 205, 211, 212,
221, 305, 311, 312 & 347).
3. The phase lock pulse is input into a phase indeterminate circuit
element which generates an adjusted output signal. (Specification 9 & 10, ¶
[0026] & [0030]; Figs. 2A & 3A; elements 221, 230, 231, 330 & 332).
4. The phase lock signal is provided to a chip to produce the phase
lock pulse, which is used at the next edge of the output of the phase
indeterminate circuit element to produce a signal with a known phase
relationship to the clock signal. (Specification 10 & 11, ¶ [0032]; Fig. 3B;
elements 311, 312, 347, 332A & 332B).
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5. Pierschel is directed to a static frequency divider, where the divider
ratio, of the frequency divider portion, D-type flip-flops A and B, can be
switched using synchronous D-type flip-flops C, D, E and F. Both the
synchronous block and the frequency divider portion are connected to a
frequency clock (CLK & CLK’) and the synchronous block receives a
control input St and St’. (Abstract; col. 2, ll. 58-67; Fig. 1).
6. The Examiner has indicated that the output of the flip-flop F is a
phase clock pulse, where that output is identified as a pulse and is locked in
phase with the clock signal. (Answer 3 & 7).
7. Pierschel discloses that signal SW A is the change over switching
signal of the synchronous D-type flip-flop F connected to the divider D-type
flip-flop A, where that signal changes its level state in the event of a signal
change. (Col. 3, ll. 18-20, col. 4, ll. 25-29; Fig. 4).
8. Appellant contends that Pierschel provides no signal that can
reasonably be construed as the phase lock pulse as recited in claim 1. (Reply
Br. 6)

PRINCIPLES OF LAW
“A claim is anticipated only if each and every element as set forth in
the claim is found, either expressly or inherently described, in a single prior
art reference.” Verdegaal Bros., Inc. v. Union Oil Co. of California, 814
F.2d 628, 631, (Fed. Cir. 1987).
The Examiner bears the initial burden of presenting a prima facie case
of obviousness. In re Oetiker, 977 F.2d 1443, 1445, 24 USPQ2d 1443, 1444
(Fed. Cir. 1992). If that burden is met, then the burden shifts to the
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Appellant to overcome the prima facie case with argument and/or evidence.
See Id.
Although claims of issued patents are interpreted in light of the
specification, prosecution history, prior art and other claims, this is not the
mode of claim interpretation to be applied during examination. During
examination, the claims must be interpreted as broadly as their terms
reasonably allow. In re American Academy of Science Tech Center, 367 F.3d
1359, 1369 (Fed. Cir. 2004). However, the broadest reasonable
interpretation of the claims must also be consistent with the interpretation
that those skilled in the art would reach. In re Cortright, 165 F.3d 1353,
1358, (Fed. Cir. 1999). It is the use of the words in the context of the written
description and customarily by those skilled in the relevant art that
accurately reflects both the “ordinary” and the “customary” meaning of the
terms in the claims. Ferguson Beauregard/Logic Controls v. Mega Systems,
350 F.3d 1327, 1338, (Fed. Cir. 2003).

ANALYSIS
Our analysis of the rejections turns on the interpretation of terms
within the claims. While it is acknowledged that Appellant has raised many
potential points of distinction on appeal, we need only consider a single
element to determine the efficacy of the rejections.
Independent claim 1 recites that the phase lock circuitry is configured
to generate a phase lock pulse. Independent claims 10, 19 and 28-33
similarly recite a limitation directed to generating a phase lock pulse. The
specification of the instant application does not specifically define a pulse,
but does describe a “pulse generator” and Figure 3B illustrates a “lock phase
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pulse” (347) that comports with an interpretation that would likely be
supplied by one of ordinary skill in the art. A pulse should have a rising
edge and a falling edge with a finite period in between. This can be
contrasted with the “lock phase” signal that indicates a level change. The
latter signal would not be considered to be a pulse within the normal,
ordinary or customary meaning of the word.
Pierschel discloses that the output signal of the synchronous D-type
flip-flop F is a level change. (Finding of Fact 7). Review of the description
and illustrations in Pierschel does not inform that the output of flip-flop F is
a pulse, contrary to the findings of the Examiner. (Finding of Fact 6).
While Pierschel does disclose trains of pulses, such as the clock signal or the
output signals of the frequency divider, the production of a phase lock pulse
is nowhere disclosed therein. In addition, since the output of flip-flop F is a
change-over switching signal, it is not clear why any type of pulse should be
substituted for such a change-over switching signal.
Since Pierschel fails to teach that a phase lock pulse is produced
and/or input into the frequency divider portion, the disclosure of Pierschel
cannot be said to anticipate the independent claims. As such, the
anticipation rejection of claims 1-3, 5, 6, 8, 10-12, 14, 15, 17, 19-24 and 28-
33 is improper and must be reversed. For at least their dependence on
claims 1 and 10, the obviousness rejection of claims 9 and 18 are likewise
improper and also reversed.

CONCLUSION OF LAW
We conclude that Appellant has shown that the Examiner erred in
rejecting claims 1-3, 5, 6, 8-12, 14, 15, 17-24 and 28-33.
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DECISION
The Examiner's rejection of claims 1-3, 5, 6, 8-12, 14, 15, 17-24 and
28-33is reversed.

REVERSED

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