Ex Parte Kadosh

Board of Patent Appeals and Interferences

May 7, 2008

10284969 (B.P.A.I. May. 7, 2008)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte DANIEL KADOSH
____________

Appeal 2007-4442
Application 10/284,9691
Technology Center 2100
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Decided: May 7, 2008
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Before JAMES D. THOMAS, HOWARD B. BLANKENSHIP,
and JEAN R. HOMERE, Administrative Patent Judges.

HOMERE, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134 from the Examiner’s
rejection of claims 1 through 27. We have jurisdiction under 35 U.S.C.
§ 6(b). We affirm.

1 Filed on Oct. 31, 2002. The real party in interest is Advanced Micro
Devices, Inc.
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Application 10/284,969

The Invention
Appellant invented a manufacturing method and system for
processing semiconductor wafers. (Spec. 6.) As depicted in Figure 1, the
system (10) includes a plurality of process tools (30), and metrology tools
(50). The system (10) further includes a process controller (100) that
interfaces with a simulation unit (110) via a network (20). Upon receiving
fabrication data for a workpiece being processed, the simulation unit (110)
simulates a future processing by using the fabrication data to predict one or
more electrical parameters that would more closely match a target value in
the simulated future processing environment. The system (10) subsequently
uses the predicted electrical parameter in one of the tools to process the
workpiece. (Spec. 8.)
Independent claim 1 further illustrates the invention. It reads as
follows:
1. A method, comprising:
processing a workpiece in a manufacturing system including a plurality of
tools;
retrieving workpiece fabrication data related to the processing;
simulating future processing in the manufacturing system based on the
workpiece fabrication data;
predicting at least one electrical parameter for the future processing based on
the simulating; and
processing the workpiece in at least one of the tools based on the predicted
electrical parameter.
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. In rejecting the claims on appeal, the Examiner relied upon the
following prior art:

Steffan2 US 6,041,270 Mar. 21, 2000
Steffan3 US 6,154,711 Nov. 28, 2000
Miller US 2004/0040001A1 Feb. 26, 2004
(Filed Aug. 22, 21002)

The Examiner rejected the claims on appeal as follows:
1. Claims 1 through 7 and 9 through 27 stand rejected under
35 U.S.C. § 102(e) as being anticipated by Miller.
2. Claims 1 through 9, 11 through 22, and 24 through 27 stand
rejected under 35 U.S.C. § 102(b) as being anticipated by Steffan_270.
3. Claims 1 through 9, 11 through 22, and 24 through 27 stand
rejected under 35 U.S.C. § 102(b) as being anticipated by Steffan_711.
4. Claims 10 and 23 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Staffan_270.
5. Claims 10 and 23 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Staffan_711.

FINDINGS OF FACT
The following findings of fact (FF) are supported by a preponderance
of the evidence.

2 This patent (Steffan_270) terminally disclaims the subject matter of
Steffan_771.
3 This patent (Steffan_771) terminally disclaims the subject matter of
Steffan_270).

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Application 10/284,969

Miller
1. As depicted in Figure 1, Miller discloses a manufacturing system
for processing semiconductor wafers. The system (10) includes a plurality
of process tools (30) and metrology tools (50). The system (10) further
includes a process controller (100) that communicates with a fault monitor
(110), as well as a prediction unit (130) via a network (20). (P. 2, para.
0019.)
2. As shown in Figure 2, Miller discloses that the prediction unit
(130) includes a modeling engine (122) that utilizes values specified in a
design vector (124) to predict electrical characteristics of a virtual device.
(P.4, para. 0032.) The prediction unit (130) employs the modeling engine to
collect data from the diverse tools during the fabrication process to calculate
predicted values for various electrical characteristics of a device throughout
the fabrication process. (P. 3, para. 0023.)
Steffan_270
3. Steffan_270 discloses a method for manufacturing semiconductor
wafers. As shown in Figure 3, a simulation tool (300) uses the critical
dimensions of a current process along with those of previous processes to
simulate a set of predicted wafer electrical test (WET) measurements. It
then compares the measured WET values to a set of target wafer values to
obtain a set of optimized parameters for an equipment in the next process.
(Abstract, col. 4, ll. 2-25.)

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Steffan_711
4. Steffan_711 discloses a method for manufacturing semiconductor
wafers. As shown in Figure 3, a simulation tool (300) uses the critical
dimensions of a current process along with those of previous processes to
simulate a set of predicted wafer electrical test (WET) measurements. It
then compares the measured WET values to a set of target wafer values to
obtain a set of optimized parameters for an equipment in the next process.
(Col. 4, ll. 19-39.)

PRINCIPLES OF LAW
ANTICIPATION
In rejecting claims under 35 U.S.C. § 102, “a single prior art reference
that discloses, either expressly or inherently, each limitation of a claim
invalidates that claim by anticipation.” Perricone v. Medicis
Pharmaceutical Corp., 432 F.3d 1368, 1375-76 (Fed. Cir. 2005), citing
Minn. Mining & Mfg. Co. v. Johnson & Johnson Orthopaedics, Inc., 976
F.2d 1559, 1565 (Fed. Cir. 1992). “Anticipation of a patent claim requires a
finding that the claim at issue ‘reads on’ a prior art reference.” Atlas Powder
Co. v. IRECO, Inc., 190 F.3d 1342, 1346 (Fed Cir. 1999) (“In other words, if
granting patent protection on the disputed claim would allow the patentee to
exclude the public from practicing the prior art, then that claim is
anticipated, regardless of whether it also covers subject matter not in the
prior art.”) (internal citations omitted).

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OBVIOUSNESS
Appellants have the burden on appeal to the Board to demonstrate
error in the Examiner’s position. See In re Kahn, 441 F.3d 977, 985-86
(Fed. Cir. 2006) (“On appeal to the Board, an applicant can overcome a
rejection [under § 103] by showing insufficient evidence of prima facie
obviousness or by rebutting the prima facie case with evidence of secondary
indicia of nonobviousness.”) (quoting In re Rouffet, 149 F.3d 1350, 1355
(Fed. Cir. 1998)).
The Supreme Court in Graham v. John Deere Co., 383 U.S. 1, 17-18
(1966), stated that the following factual inquiries underpin any
determination of obviousness:
Under § 103, [1] the scope and content of the prior art are to be
determined; [2] differences between the prior art and the claims
at issue are to be ascertained; and [3] the level of ordinary skill
in the pertinent art resolved. Against this background, the
obviousness or nonobviousness of the subject matter is
determined. Such (4) secondary considerations as commercial
success, long felt but unsolved needs, failure of others, etc.,
might be utilized to give light to the circumstances surrounding
the origin of the subject matter sought to be patented. As
indicia of obviousness or nonobviousness, these inquiries may
have relevancy.
Where the claimed subject matter involves more than the simple
substitution of one known element for another or the mere application of a
known technique to a piece of prior art ready for the improvement, a holding
of obviousness must be based on “an apparent reason to combine the known
elements in the fashion claimed.” KSR Int’l v. Teleflex, Inc., 127 S. Ct.
1727, 1740-41 (2007). That is, “there must be some articulated reasoning
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with some rational underpinning to support the legal conclusion of
obviousness.” Id., 127 S. Ct. at 1741, (quoting In re Kahn, 441 F.3d 977,
988 (Fed. Cir. 2006)). Such reasoning can be based on interrelated teachings
of multiple patents, the effects of demands known to the design community
or present in the marketplace, and the background knowledge possessed by a
person having ordinary skill in the art. KSR, 127 S. Ct. at 1740-41.

ANALYSIS
102 Rejections
Claims 1-7 and 9-27
Independent claim 1 recites in relevant part simulating a future
processing using fabrication data of a workpiece to predict one or more
electrical parameters in the future processing. (App. Br., Claims Appendix.)
Appellant argues that Miller does not teach these limitations. (App. Br. 5-6.)
The Examiner, in response, avers that Miller’s prediction unit inherently
teaches the simulation of a future processing by performing modeling and
prediction of electrical characteristics. (Ans. 5.)
Therefore, the pivotal issue before us is whether one of ordinary skill
in the art would find that the prediction of electrical characteristics
performed by Miller’s modeling engine teaches the simulation of a future
processing, as claimed. We answer this inquiry in the affirmative.
We begin by considering the scope and meaning of “simulation of
future processing” which must be given its broadest reasonable
interpretation consistent with Appellant’s disclosure, as explained in In re
Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997):
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[T]he PTO applies to the verbiage of the proposed claims the
broadest reasonable meaning of the words in their ordinary
usage as they would be understood by one of ordinary skill in
the art, taking into account whatever enlightenment by way of
definitions or otherwise that may be afforded by the written
description contained in the applicant's specification.
Id. at 1054. See also In re Zletz, 893 F.2d 319, 321 (Fed. Cir. 1989) (stating
that “claims must be interpreted as broadly as their terms reasonably allow.”
Appellant’s Specification states the following:
By simulating the manufacturing processes, the simulation unit 110 is
capable of predicting electrical characteristics of the devices
fabricated by the manufacturing system 10. The simulation unit 110 is
also capable of providing data related to subsequent process steps to
allow the completed devices to meet a predetermined electrical
characteristic target… . Typically, the simulation unit 110 simulates a
series of process steps for the wafer being fabricated. In essence, the
simulation unit 110 operates as a virtual fabrication facility. The user
may specify that certain fabrication parameters be fixed, and that
others may be variable. The simulation unit 110 manipulates the
variable parameters during the simulation process to attempt to
determine settings for the variable parameters that achieve the
specified performance targets… . The simulation unit 110 then
simulates the fabrication process and varies the one or more
designated variable parameters to determine the parameter values that
would most closely achieve the saturation current target.
(Spec. 8, ll. 4-23.)
Our reviewing court further states, “the ‘ordinary meaning’ of a claim
term is its meaning to the ordinary artisan after reading the entire patent.”
Phillips v. AWH Corp., 415 F.3d 1303, 1321 (Fed. Cir. 2005).
Upon reviewing Appellant’s Specification, we fail to find any
definition of the term “simulation of a future processing” that is different
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from the ordinary meaning. We find the ordinary meaning of the term
“simulation” is best found in the dictionary.4 Therefore, we interpret the
claimed limitation of “simulating future processing” as the imitation of a
future processing by using a mathematical model (that processes workpiece
fabrication data) to predict an electrical parameter (for future processing).
As detailed in the findings of facts section above, Miller discloses a
prediction unit that employs a modeling engine to collect data from diverse
tools during the fabrication process of a device to calculate predicted values
for various electrical characteristics of the device. (FF. 2.) One of ordinary
skill in the art would readily recognize that Miller’s prediction unit, by using
a mathematical model that processes collected fabrication data to calculate
predicted electrical values for a device, teaches the claimed simulation of a
future processing to predict an electrical value. Thus, under our
interpretation above, Miller’s prediction unit teaches simulating the future
processing by using fabrication data of a device being processed to predict
electrical values therefor.
Further, as noted above, Appellant merely recites the afore-cited
language of claim 1, and alleges that the recited limitations are not found in
Miller. (App. Br. 5-6.) However, Appellant has failed to particularly
address the Examiner’s specific findings of fact that Miller’s prediction unit
inherently performs the claimed simulation of a future processing. (Ans. 5.)

4 Simulation is the imitation of a physical process by a program that causes a
computer to respond to data and conditions as though it were the process
itself. It uses mathematical description to construct a model of the subject,
and then uses more mathematics to evaluate different situations involving
the subject. (Microsoft Press Computer Dictionary, Second Edition, 1993,
pp. 361-62.)
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Appellant’s gratuitous allegations without providing a scintilla of evidence
are insufficient to overcome the Examiner’s prima facie case of anticipation.
“[A]fter the PTO establishes a prima facie case of anticipation based on
inherency, the burden shifts to appellant to ‘prove that the subject matter
shown to be in the prior art does not possess the characteristic relied on.’”
In re King, 801 F.2d 1324, 1327(Fed. Cir. 1986) (quoting In re Swinehart,
439 F.2d 210, 212-13, (CCPA 1971)). See also MPEP §§ 2112 (IV.), (V.).
It follows that Appellant has not shown that the Examiner erred in
finding that Miller anticipates independent claim 1.
Appellant does not provide separate arguments with respect to the
rejection of claims 2 through 7 and 9 through 27. Therefore, we select claim
1 as being representative of the cited claims. Consequently, claims 2
through 7 and 9 through 27 fall together with representative claim 1. 37
C.F.R. § 41.37(c)(1)(vii).

Claims 1-9, 11-22, and 24 through 27
Appellant argues that neither Steffan_270 nor Steffan_711 (Steffan,
hereinafter) teaches simulating a future processing using fabrication data of
a workpiece to predict one or more electrical parameters in the future
processing. (App. Br. 6-7.) In response, the Examiner submits that
Steffan’s teachings disclose the claimed limitations. (Ans. 6-8.) We agree
with the Examiner.
As detailed in the Findings of Fact above, both Steffan patents
disclose simulating a future processing by using, inter alia, fabrication data
of a workpiece currently being processed in order to predict the electrical
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values to be used in the future processing. (FF. 3-4.) Therefore, the
ordinarily skilled artisan would aptly recognize that each Steffan patent
clearly teaches the claimed simulation of a future processing based on the
workpiece fabrication data. It follows that Appellant has not shown that the
Examiner erred in finding that Steffan anticipates claim 1.
Appellant does not provide separate arguments with respect to the
rejection of claims 2 through 9, 11 through 22, and 24 through 27.
Therefore, we select claim 1 as being representative of the cited claims.
Consequently, claims 2 through 9, 11 through 22, and 24 through 27 fall
together with representative claim 1. 37 C.F.R. § 41.37(c)(1)(vii).

103 Rejections
Claims 10 and 23
Appellant argues that the Steffan does not teach simulating a future
processing using fabrication data of a workpiece to predict one or more
electrical parameters in the future processing, as recited in claims 1 and 14.
Therefore, Steffan does not render claims 10 and 23 unpatentable since they
incorporate this limitation by virtue of their dependency on claims 1 and 14,
respectively. (App. Br. 8-9.) This argument is unavailing. In our discussion
of claims 1 and 14 above, we found that Steffan clearly teaches the cited
limitation.
Further, Appellant argues that there is insufficient rationale to modify
Steffan as proffered by the Examiner. (Id.) We do not agree. The Supreme
Court has held that in analyzing the obviousness of combining elements, a
court need not find specific teachings, but rather may consider "the
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background knowledge possessed by a person having ordinary skill in the
art" and "the inferences and creative steps that a person of ordinary skill in
the art would employ." See KSR Int’l, 127 S. Ct. at 1740-41. To be
nonobvious, an improvement must be "more than the predictable use of prior
art elements according to their established functions." Id. at 1740. As set
forth in our discussion of claim 1 above, Steffan’s teachings in each patent
demonstrate that simulating a future processing using present fabrication
data is conventionally performed in a wafer manufacturing process for the
known purpose of predicting an electrical characteristic for future use.
Additionally, Appellant alleges that Steffan teaches away from
predicting at least one electrical parameter for future processing based on the
simulation. Beyond these mere allegations, Appellant has provided no
further explanation or evidence to substantiate his position. In our view, such
gratuitous allegations are insufficient to overcome the Examiner’s prima
facie case of obviousness. It therefore follows that Appellant has not shown
that the Examiner erred in concluding that each Steffan patent renders claims
10 and 23 unpatentable.

SUMMARY and DECISON
Appellant has not shown that the Examiner erred in concluding that:
1. Miller anticipates claims 1 through 7, and 9 through 27 under
35 U.S.C. § 102(e).
2. Steffan_270 anticipates claims 1 through 9, 11 through 22, and
24 through 27 under 35 U.S.C. § 102(b).
3. Steffan_711 anticipates claims 1 through 9, 11 through 22, and
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24 through 27 under 35 U.S.C. § 102(b).
4. Steffan_270 renders claims 10 and 23 unpatentable under
35 U.S.C. § 103(a).
5. The Steffan_711 renders claims 10 and 23 unpatentable under
35 U.S.C. § 103(a).
Therefore we affirm these rejections.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

pgc

WILLIAMS, MORGAN & AMERSON
10333 RICHMOND, SUITE 1100
HOUSTON TX 77042

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