Ex Parte Jung et al

Board of Patent Appeals and Interferences

Aug 29, 2011

10969995 (B.P.A.I. Aug. 29, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/969,995 10/22/2004 Sung Mun Jung 602-0039 6631
60803 7590 08/29/2011
SHERR & VAUGHN, PLLC
620 HERNDON PARKWAY
SUITE 320
HERNDON, VA 20170
EXAMINER
DIAZ, JOSE R
ART UNIT PAPER NUMBER
2815
MAIL DATE DELIVERY MODE
08/29/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte SUNG MUN JUNG and DONG OOG KIM
____________

Appeal 2009-014557
Application 10/969,995
Technology Center 2800
____________

Before LANCE LEONARD BARRY, ST JOHN COURTENAY III, and
ANDREW J. DILLON, Administrative Patent Judges.

DILLON, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 8, and 10-19, claims 1-7 and 9 having been cancelled.
We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
STATEMENT OF THE CASE
Appellants’ invention is a non-volatile memory cell which includes a
semiconductor substrate of a first conductivity type having device isolation
regions and active regions defined therein. A first well of a second
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Application 10/969,995

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conductivity type is provided in the semiconductor substrate and a plurality
of second wells are formed inside the first well, with a plurality of ONO
structures formed over the second wells. See Abstract.

Claim 8 is illustrative with key disputed limitations emphasized:
8. A method for fabricating an embedded non-volatile
memory comprising:

providing a semiconductor substrate having a first conductivity type;

forming device isolation regions in the semiconductor substrate;

forming a first well having a second conductivity inside the
semiconductor substrate;

forming a plurality of second wells having the first conductivity type
inside the first well between the device isolation regions after forming
the device isolation regions, wherein the plurality second wells are
formed to extend in a direction parallel to a bit line direction and are
surrounded by the device isolation regions and the first well, wherein
forming the plurality of second wells comprises injecting impurity
ions into the semiconductor substrate between the device isolation
regions after covering the device isolation regions using a photoresist
mask;

forming a plurality of ONO structures by sequentially forming a first
oxide film, a nitride film, and a second oxide film over each of the
second wells; and

forming a plurality of gates on the ONO structures, wherein the
plurality of gates are formed to extend in a direction parallel to a word
line direction.

Appeal 2009-014557
Application 10/969,995

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The Examiner relies on the following as evidence of unpatentability:
Yaegashi US 6,894,931 B2 May 17, 2005
(filed Mar. 21, 2003)
Li US 6,545,310 B2 Apr. 8, 2003
Huang US 6,757,208 B1 Jun. 29, 2004
(filed Sep. 22, 2003)
Lee US 2003/0032242 A1 Feb. 13, 2003

THE REJECTIONS
1. The Examiner rejected claims 8, 10-12, 18 and 19 under 35 U.S.C.
§ 103(a) as unpatentable over Yaegashi, Li and Huang. Ans. 3-6.1
2. The Examiner rejected claims 13-17 under 35 U.S.C. § 103(a) as
unpatentable over Yaegashi, Li, Huang and Lee. Ans. 6-7.

CONTENTIONS
Regarding representative claim 8, the Examiner finds that Yaegashi
discloses a semiconductor substrate of a first conductivity type having
device isolation regions and active regions therein, with a first well of a
second conductivity type in the semiconductor substrate. The Examiner also
finds that Yaegashi discloses a second well of a first conductivity type
having a plurality of ONO structures formed thereover, having gates formed
on each ONO structure. The Examiner finds that Li teaches a plurality of
second wells being formed in parallel with a bit line which are surrounded
by device isolation

1 Throughout this opinion, we refer to the Appeal Brief filed January 18,
2009 and the Examiner’s Answer mailed May 22, 2009.
Appeal 2009-014557
Application 10/969,995

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regions and the first well, but finds that Huang teaches that it was well
known to form second wells within first wells by using a photoresist mask to
protect portions of the substrate during ion implantation. Ans. 4-6.
Appellants argue that Yaegashi does not disclose a plurality of second
wells which are formed inside the first well between the device isolation
regions or that the second wells are formed by injecting impurity ions into
the substrate after covering the device isolation regions using a photoresist
mask. Br. 12. Appellants also argue that although Li discloses multiple
P-type wells separated by device isolation regions, there is no suggestion
within Li of how the P-type wells are formed. Finally, Appellants argue that
Huang fails to teach the forming of wells between device isolation regions.
Br. 12-13.
The issues before us, then, are as follows:

ISSUES
1. Under § 103, has the Examiner erred in rejecting claims 8, 10-12,
18, and 19 by finding that Yaegashi, Li and Huang collectively would have
taught or suggested (1) a method for fabricating a non-volatile memory on a
semiconductor substrate by forming device isolation regions in the substrate,
forming a first well in the substrate and then forming a plurality of second
wells inside the first well by injecting impurity ions into the substrate after
covering the device isolation regions with a photoresist mask, and (2)
forming a plurality of ONO structures with gates over each of the second
wells?
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Application 10/969,995

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2. Under § 103, has the Examiner erred in rejecting claims 13-17 by
finding that Yaegashi, Li, Huang and Lee collectively would have taught or
suggested the specific film thickness ranges set forth in those claims for the
method set forth in claim 8?

FINDINGS OF FACT
We find that the following enumerated findings of fact (FF) are
supported by at least a preponderance of the evidence. Ethicon, Inc. v.
Quigg, 849 F.2d 1422, 1427 (Fed. Cir. 1988) (explaining the general
evidentiary standard for proceedings before the Office).
1. Yaegashi discloses a non-volatile semiconductor memory formed
on a semiconductor substrate 121of a first conductivity type (P-
type) having a first well 122 of a second conductivity type (N-
type) and a second well 123 of the first conductivity type (P-type)
formed to extend along each bit line within the first well 122.
Yaegashi, figs. 39B and 40A, col. 36, ll. 38-44.
2. Yaegashi discloses a plurality of ONO structures, each having a
gate, formed over each second well 123. Yaegashi, figs. 39B and
40A, col 36, ll. 48-60.
3. Li discloses a plurality of P-type wells (46, 47) formed within an
N-type well 48, between isolation regions 42. Li, fig. 4, col 5, ll.
31-51.
4. Huang discloses that the defining of well regions using photoresist
masks and ion dopants is conventional in the art. Huang, col. 3, ll.
30-44.
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ANALYSIS
Based on the Appellants' arguments and the dependencies of the
claims, we will decide the appeal of claims 10-19 on the basis of claim 8.
See 37 C.F.R. § 41.37(c)(1)(vii).
Appellants dispute the Examiner’s rejection of representative claim 8
by attacking the cited references individually, despite the fact that the
rejection is based upon a combination of those references. Br. 12-17.
For example, Appellants argue that Yaegashi fails to disclose a
plurality of second wells formed inside a first well, or the forming of those
second wells utilizing the injection of ions and a photoresist mask. Id at 12.
We are not persuaded by such piecemeal attacks. As found by the
Examiner, Yaegashi, discloses in Figure 40A, a single second well which is
formed within a first well. Ans. 4. We find that Figure 40A is a sectional
view of Figure 39B, taken along one bit line and, presumably, each bit line
within Figure 39B will have an associated second well. (FF1).
Nevertheless, we find the Examiner has cited Li for a teaching that multiple
P-type wells 46 and 47 may be formed within a first N-type well. Ans. 5.
Our findings support that position. (FF3).
In like manner, Appellants attack Li based upon a failure to disclose
how the multiple P-type wells are formed, or that the P-type wells are inside
the N-type well (Br. 12), despite the fact the Examiner has expressly relied
upon Huang for a teaching that it was conventional to utilize a photoresist
mask and ion dopants to define wells (Ans. 5) which is consistent with our
findings, (FF4) and has relied upon Yaegashi for the teaching that forming
P-type well within N-type wells was known in the art. Ans. 4.
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Appellants argue the rejection of claims 13-17 for the same reasons
set forth above with respect to claim 8, and for the reasons we have
enumerated above we do not find those arguments persuasive.
We find Appellants piecemeal attack on the references unpersuasive
and we hold that the Examiner did not err in rejecting representative claim 8
and claims 10-19 not separately argued with particularity.

CONCLUSION
The Examiner did not err in rejecting claims 8 and 10-19 under § 103.

ORDER
The Examiner’s decision rejecting claims 8 and 10-19 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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