Ex Parte Jung et al

Board of Patent Appeals and Interferences

Jan 19, 2011

11019315 (B.P.A.I. Jan. 19, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/019,315 12/23/2004 Sung Mun Jung 604-0008 4286
60803 7590 01/20/2011
SHERR & VAUGHN, PLLC
620 HERNDON PARKWAY
SUITE 320
HERNDON, VA 20170
EXAMINER
CHEN, JACK S J
ART UNIT PAPER NUMBER
2893
MAIL DATE DELIVERY MODE
01/20/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte SUNG MUN JUNG and JUM SOO KIM
____________________

Appeal 2009-008540
Application 11/019,3151
Technology Center 2800

____________________

Before MAHSHID D. SAADAT, MARC S. HOFF,
and THOMAS S. HAHN, Administrative Patent Judges.

HOFF, Administrative Patent Judge.

DECISION ON APPEAL2

1 The real party in interest is Dongbu HiTek Co., Ltd.
2 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or filing a request for rehearing, as
recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE” (paper
delivery mode) or the “NOTIFICATION DATE” (electronic delivery mode)
shown on the PTOL-90A cover letter attached to this decision.
Appeal 2009-008540
Application 11/019,315

STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from a Non-Final
Rejection of claims 1-9. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
Appellants’ invention relates to a method of fabricating a flash
memory device wherein the coupling ratio is raised by shortening the
interval between floating gates using a spacer (Abstract). A trench isolation
layer is formed in a semiconductor substrate by filling a trench with high
density plasma oxide (Spec. ¶ [0038]). A tunnel oxide layer is formed on
the active area defined by the trench isolation layer (Spec. ¶ [0039]). A first
conductor layer is formed over the substrate and represents a floating gate
(Spec. ¶ [0040]). An insulating layer pattern is formed in the first conductor
layer and a photoresist pattern is formed on the insulating layer such that its
pattern has openings exposing portions of the insulating layer (Spec. ¶
[0041]). The insulating layer pattern is made of plasma nitride to prevent
undercut from occurring at the trench isolation layer when the plasma nitride
layer is removed at a later step of the process (Spec. ¶ [0041]). A spacer
insulating layer is formed on the insulating layer pattern and the exposed
portions of the first conductor layer (Spec. ¶ [0043-44]). The spacer
insulating layer is anisotropically etched to form a spacer on a sidewall of
the insulating layer pattern (Spec. ¶ [0045]). The exposed portion of the first
conductor layer is removed using the spacer as an etch mask (Spec. ¶
[0046]). The insulating layer pattern and the spacer is removed, forming a
gate-to-gate insulating layer over the substrate (Spec. ¶ [0047]). Last, a
second conductor layer is formed on the gate-to-gate insulating layer (Spec.
[0048]).
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Appeal 2009-008540
Application 11/019,315

Claim 1 is exemplary:
1. A method of fabricating a flash memory device, comprising the steps
of:
forming a trench isolation layer defining an active area of a
semiconductor substrate;
forming a tunnel oxide layer on the active area of the semiconductor
substrate such that a height of the tunnel oxide layer is not lower than a
height of the trench isolation layer;
forming a first conductor layer for a floating gate directly on the
tunnel oxide layer and the trench isolation layer;
forming an insulating layer pattern on the first conductor layer, the
insulating layer pattern having a predetermined etch selectivity with the
trench isolation layer to expose a portion of the first conductor layer;
forming a spacer on a sidewall of the insulating layer pattern; forming
a first conductor layer pattern exposing a portion of the trench isolation layer
by removing the exposed portion of the first conductor layer using the spacer
as an etch mask;
removing the insulating layer pattern and the spacer;
forming a gate-to-gate insulating layer on the first conductor layer
pattern and the trench isolation layer; and
forming a second conductor layer for a control gate on the gate-to-
gate insulating layer.

The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Hsieh US 6,326,263 B1 Dec. 4, 2001
Shin US 6,482,728 B2 Nov. 19, 2002
Wu US 2004/0094795 A1 May 20, 2004

Claims 1-9 stand rejected under 35 U.S.C. 112, first paragraph, as
failing to comply with the written description requirement.
Claims 1 and 6 stand rejected under 35 U.S.C. § 102(e) as being
anticipated by Wu.
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Appeal 2009-008540
Application 11/019,315

Claim 1 stands rejected under 35 U.S.C. § 102(b) as being anticipated
by Shin.
Claim 1 stands rejected under 35 U.S.C. § 102(a, b, or e) as being
anticipated by “applicant’s admitted prior art.”
Claims 2-5 and 7-9 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Wu in view of Hsieh.

ISSUE
Appellants contend that the written description requirement can be
satisfied by having described the claimed invention through “words” or
“drawings” (App. Br. 11). Appellants assert that Figure 7 clearly discloses
“a height of the tunnel oxide layer [210] is not lower than a height of the
trench isolation layer [204]” (App. Br. 11).
Appellants’ contentions present us with the following dispositive
issue: Does the Specification provide adequate support for a method of
fabricating a flash memory device including a trench isolation layer and a
tunnel oxide, wherein the “height of the tunnel oxide layer is not lower than
a height of the trench isolation layer”?

FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
The Invention
1. A trench isolation layer 204 is formed in a device isolation area
of a semiconductor substrate 200 by general trench isolation (¶ [0038]). The
trench is filled up with a filling insulating layer to form trench isolation layer
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Appeal 2009-008540
Application 11/019,315

204 (¶ [0038]). Subsequently, a tunnel oxide layer 210 is formed on the
active area 202 of the semiconductor substrate 200 (¶ [0039]).

PRINCIPLES OF LAW
Under the written description requirement of 35 U.S.C. § 112, the
disclosure of the application relied upon must reasonably convey to one of
ordinary skill in the art that, as of the filing date of the application, the
inventor had possession of the later-claimed subject matter. Vas-Cath Inc. v.
Mahurkar, 935 F.2d 1555, 1563 (Fed. Cir. 1991). "One shows that one is 'in
possession' of the invention by describing the invention, with all its claimed
limitations, not that which makes it obvious." Lockwood v. American
Airlines, Inc., 107 F.3d 1565, 1572 (Fed. Cir. 1997) (emphasis in original).
Although "the meaning of terms, phrases, or diagrams in a disclosure
is to be explained or interpreted from the vantage point of one skilled in the
art, all the limitations must appear in the specification." Id. The
specification need not describe the claimed subject matter in exactly the
same terms as used in the claims, but it must contain an equivalent
description of the claimed subject matter. Id.
Subject matter not disclosed in the original application that is added to
an original claim may be rejected on the ground that it recites elements
without support in the original disclosure under 35 U.S.C. 112, first
paragraph, Waldemar Link, GmbH & Co. v. Osteonics Corp. 32 F.3d 556,
559 (Fed. Cir. 1994); In re Rasmussen, 650 F.2d 1212, 1215 (CCPA 1981).
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Application 11/019,315

ANALYSIS
REJECTION OF CLAIMS 1-9 UNDER 35 U.S.C. § 112, FIRST PARAGRAPH
Appellants’ arguments do not persuade us that the claims satisfy the
written description requirement of 35 U.S.C. § 112, ¶ 1.
Independent claim 1 recites a combination, including, inter alia “a
height of the tunnel oxide layer is not lower than a height of the trench
isolation layer” (emphasis added).
The prosecution history shows that claim 1, as originally filed, does
not include the aforementioned claim limitation. Additionally, this language
does not appear in Appellants’ originally filed Specification. Rather, the
Specification solely discloses that a trench isolation layer 204 and a tunnel
oxide layer 210 are formed without any disclosure of their heights relative
one to another (accord FF 1). Specifically, with reference to Figure 4, the
trench isolation layer 204 is formed in a device isolation area of a
semiconductor substrate 200 by general trench isolation (FF 1). The trench
is filled with a filling insulating layer to form trench isolation layer 204 (FF
1). Subsequently, a tunnel oxide layer 210 is formed on the active area 202
of the semiconductor substrate 200 (FF 1).
Regarding the interpretation of the term “height” of a layer, the
Specification is silent as to the definition of the term. Appellants’ response
to the rejection does not define the “height” of a layer as it relates to the
drawing in Figure 7. Appellants merely contend that Figure 7 “clearly
discloses ‘a height of the tunnel oxide layer [210] is not lower than a height
of the trench isolation layer [204],’” without illustrating the measurement of
the layer height by annotating the drawing (App. Br. 11).
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Appeal 2009-008540
Application 11/019,315

Our reviewing court states, “the ‘ordinary meaning’ of a claim term is
its meaning to the ordinary artisan after reading the entire patent.” Phillips
v. AWH Corp., 415 F.3d 1303, 1321 (Fed. Cir. 2005).
Figure 4 with the Examiner’s annotations for “H1, Height of the
tunnel oxide layer” and “H2, Height of the trench isolation layer” including
associated arrows (Ans. 4) is reproduced below:

Figure 4 is a cross-sectional diagram explaining a method of
fabrication a flash memory device.
Figures 4-7 show that the “heights” of layers 204 and 210 relative to
one another, as defined by the Examiner, do not support the claim limitation
at issue. In particular, as illustrated supra, the Examiner finds that the
height, H1, of the tunnel oxide layer 210 is defined by measuring the depth
of the layer from the base of the layer to the top of the layer (Ans. 4). The
Examiner finds that the definition of “height” is “the distance from the base
of something to the top” (Ans. 10). More particularly, the Examiner finds
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Application 11/019,315

that the height, H1, of tunnel oxide layer 210 is less than the height, H2, of
the trench isolation layer 204 (Ans. 4). The Examiner concludes that the
shown height of the tunnel oxide is lower than the height of the trench
isolation layer; and therefore, there is no support in the Specification for the
claim limitation at issue, “a height of the tunnel oxide layer is not lower than
a height of the trench isolation layer.”
Figure 7 with the Examiner’s annotations for “Height of tunnel oxide
layer 210” and “Height of the trench isolation layer 204” including
associated arrows and lines (Ans. 11) is reproduced below.

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Appeal 2009-008540
Application 11/019,315

Figure 7 is a cross-sectional diagram explaining a method of
fabrication a flash memory device.
In response to Appellants’ argument, the Examiner further finds with
reference to Figure 7 shown supra that “[o]ne having ordinary skill in the art
can interpret the term ‘height’ in its plain meaning as ‘the distance from the
base of something to the top’” (Ans. 10). As illustrated, the Examiner finds
that the height of the tunnel oxide layer 210 is less than the height of the
trench isolation layer 204 (Ans. 11-12). We agree with the Examiner’s
conclusion that the claim recitation “a height of the tunnel oxide layer is not
lower than a height of the trench isolation layer” is not supported by Figure
7, nor is it supported by the Specification as originally filed (Ans. 12).
We therefore conclude that the mere drawing disclosure for an
unspecified height of the tunnel oxide layer in comparison to that of the
trench isolation layer is not legally sufficient disclosure of the claim
language, “a height of the tunnel oxide layer is not lower than a height of the
trench isolation layer.” Therefore, Appellants have not demonstrated error
in the rejection of claims 1-9 under § 112, ¶ 1 and we will sustain the
rejection.3

CONCLUSION
The Specification does not provide adequate support for a method of
fabricating a flash memory device including a trench isolation layer and a

3 Because we affirm the rejection of all appealed claims under § 112, first
paragraph, we need not reach Appellants’ arguments with respect to the
prior art rejections.
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Appeal 2009-008540
Application 11/019,315

tunnel oxide, wherein the “height of the tunnel oxide layer is not lower than
a height of the trench isolation layer.”

ORDER
The Examiner’s rejection of claims 1-9 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).
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Appeal 2009-008540
Application 11/019,315

AFFIRMED

ELD

SHERR & VAUGHN, PLLC
620 HERNDON PARKWAY
SUITE 320
HERNDON, VA 20170
11