Ex Parte Jung

Board of Patent Appeals and Interferences

Aug 26, 2009

11024436 (B.P.A.I. Aug. 26, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte JIN HYO JUNG
____________

Appeal 2009-002124
Application 11/024,436
Technology Center 2800
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Decided: August 26, 2009
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Before JOSEPH F. RUGGIERO, MAHSHID D. SAADAT, and
KARL D. EASTHOM, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2009-002124
Application 11/024,436

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STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134 from the Final Rejection of
claims 1-8, the only claims pending (App. Br. 5).1 We have jurisdiction
under 35 U.S.C. § 6(b).
We affirm.
Appellant invented a fabricating method for nonvolatile memory
devices. The method includes removing a portion of a block oxide layer and
sidewall floating gates deposited in a field region or active area (Abstract;
Spec. ¶¶ 0022, 0027; Fig. 3).
Exemplary claim 1 follows:
1. A fabricating method of a nonvolatile memory comprising the
steps of:
forming a buffer oxide layer and a buffer nitride layer over a
semiconductor substrate;
patterning the buffer nitride layer to form sidewalls in the buffer
nitride layer;
forming sidewall floating gates on the sidewalls of the buffer nitride
layer;
forming a block oxide layer over the semiconductor substrate;
removing a portion of the block oxide layer and the sidewall floating
gates that are outside of an active area of the semiconductor substrate;
depositing a polysilicon layer over the semiconductor substrate;
patterning the polysilicon layer to form a word line;

1 Appellant’s Brief (filed Jan. 14, 2008) (“App. Br.”) and Reply Brief (filed
June 21, 2008), and the Examiner’s Answer (mailed Apr. 24, 2008)
(“Ans.”), are referenced in this opinion.
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forming sidewall spacers on sidewalls of the sidewall floating gates
and the word line; and
forming source and drain regions by implanting dopants into the
substrate.
The Examiner relies on the following prior art references:
Chang US 6,635,533 B1 Oct. 21, 2003

Mokhlesi US 2003/0157549 A1 July 21, 2005
(filed Jan. 21, 2004)
The Examiner rejected:
Claims 1-8 as indefinite under 35 U.S.C. § 112, second paragraph.
Claims 1, 2, 5, 7, and 8 as anticipated under 35 U.S.C. § 102(b) based
on Chang.
Claims 3 and 4 as obvious under 35 U.S.C. § 103(a) based on Chang.
Claim 6 as obvious under 35 U.S.C. § 103(a) based on Chang and
Mokhlesi.2
ISSUE

Appellant and the Examiner disagree over 1) whether claim 1 is
indefinite under 35 U.S.C. § 112, 2nd paragraph, and 2) whether Chang
teaches certain elements of claim 1 (compare App. Br. 9-12 with Ans. 7-12).
These disagreements raise the following two issues:
Did Appellant show that the Examiner erred in finding that claim 1 is
indefinite under 35 U.S.C. § 112, second paragraph, because Appellant

2 Notwithstanding that Mokhlesi was filed after Appellant’s foreign priority
document, Appellant did not argue that Mokhlesi does not constitute prior
art, thereby waiving any such argument for purposes of this appeal.
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failed to define an “active area” and to positively recite forming a block
oxide layer and floating gates outside of such an area prior to the recited step
of “removing a portion of the block oxide layer and the sidewall floating
gates that are outside of an active area of the semiconductor substrate”?
Did Appellant show that the Examiner erred in finding that Chang
teaches “removing a portion of the block oxide layer and the sidewall
floating gates that are outside of an active area of the semiconductor
substrate” and “forming sidewall spacers on sidewalls of the sidewall
floating gates and the word line” as set forth in claim 1?

FINDINGS OF FACT (FF)
Chang
1. Chang discloses an isolation region (not shown) in the form of a
“strip layout” to define an “active region” (col. 3, ll. 26-28). A “mask layer
204 [Fig. 2A] is patterned to form an opening 206, wherein the opening 206
is a trench substantially perpendicular to the isolation region” (col. 3, ll. 39-
41).
2. Chang discloses a self-alignment process to satisfy prior art
increased memory demands employing high integration techniques to
produce high-capacity memory devices at lower cost (col. 1, ll. 12-19; col. 4,
ll. 46-50). Voltage applied to control gates in such memory devices writes
and/or erases data/information stored therein (Chang, col. 1, ll. 25-56)
3. Chang discloses patterning a conductive spacer layer 210 and
“removing a part of the conducting spacer on the isolation region to form a
floating gate 210a” in the active area (col. 3, ll. 57-62; compare Fig. 2B with
Figs. 2C and 2D).
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4. Figures 2A to 2E schematically depict a process flow along the
cross-sectional area of the active area of one of Chang’s gate memory
devices (see FF 1 supra, col. 3, ll. 22-25).
5. Comparison of Figure 2C to Figure 2D of Chang reveals a removal
of portions of the oxide layer 214 and conductive layer 210 (forming
floating gate 210a) within the cross-sectional view of the active area
depicted (see supra FF 1-4; col. 3, l. 57 to col. 4, l. 30).
6. Chang depicts (Fig. 2E) a control gate 216 bounded on the sides by
sidewall floating gates 210a, with spacers 220 formed along the sides of the
control gate 216 and floating gates 210a, albeit not in direct contact with
either one. Chang also discloses a “conducting spacer [which] serves as the
select gate 224” (col. 4, l. 52). The spacer 224 is depicted (Fig. 2E) along
the sides and directly contacting the spacers 220 and along the sides but not
directly contacting the control gate 216.

Appellants’ Disclosure
7. Figure 3 depicts active areas 202 in the form of horizontal strips
bounded by parallel shallow trench isolation (STI) areas 201 (Spec.: ¶ 0022).
Figure 4a depicts a side-cross sectional view of isolation trenches 507 using
the STI process (Spec.: ¶ 0024).

PRINCIPLES OF LAW
“[T]he examiner bears the initial burden, on review of the prior art or
on any other ground, of presenting a prima facie case of unpatentability.” In
re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992). Appellant has the burden
on appeal to show reversible error by the Examiner in maintaining the
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rejection. See In re Kahn, 441 F.3d 977, 985-86 (Fed. Cir. 2006) (“On
appeal to the Board, an applicant can overcome a rejection by showing
insufficient evidence of prima facie obviousness or by rebutting the prima
facie case with evidence of secondary indicia of nonobviousness.”) (citation
omitted).
Under § 112, 2nd paragraph, Appellant must demonstrate that the
Examiner erred in finding that a disputed claim is not “sufficiently definite
such that those skilled in the art would understand what is being claimed
when the claim is read in light of the Specification.” Ex parte Miyazaki,
App. No. 2007-3300, slip op. at 16 (BPAI 2008) (precedential), avail. at
http://www.uspto.gov/web/offices/dcom/bpai/prec/fd073300.pdf
Under § 102, Appellant may sustain the burden on appeal by showing
that the prior art reference relied upon by the Examiner fails to disclose an
element of the claim. “It is axiomatic that anticipation of a claim under §
102 can be found only if the prior art reference discloses every element of
the claim.” In re King, 801 F.2d 1324, 1326 (Fed. Cir. 1986). “A reference
anticipates a claim if it discloses the claimed invention ‘such that a skilled
artisan could take its teachings in combination with his own knowledge of
the particular art and be in possession of the invention.’” In re Graves, 69
F.3d 1147, 1152 (Fed. Cir. 1995) (quoting In re LeGrice, 301 F.2d 929, 936
(CCPA 1962)) (emphasis omitted).
Under § 103, a holding of obviousness can be based on a
showing that “there was an apparent reason to combine the known
elements in the fashion claimed.” KSR Int’l Co. v. Teleflex Inc., 550
U.S. 398, 418 (2007).

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ANALYSIS
35 U.S.C. § 112 (second paragraph) Rejection
Appellant points to the Specification to define the term “active area”
(App. Br. 10, citing Figs. 3, 4c, 4d ; Spec. ¶¶22, 26, and 27). According to
paragraph 22, Figure 3 depicts an “active area” defined by a strip 202.
Figure 3 depicts the active area strips 202 as bounded by “shallow trench
isolation . . . areas 201” on either side thereof. Chang similarly defines an
active area as one bounded by isolation areas (compare FF 1 with FF 7). As
such, skilled artisans would have understood the meaning and scope of “an
active area” as Appellant argues (App. Br. 10), notwithstanding the
Examiner’s contention otherwise (Ans. 3, 9).
The Examiner also contends (Ans. 9) that certain implied steps for
forming a portion of the sidewall floating gates and the block oxide layer
inside and outside an active area must be recited prior to the removing step
recited in claim 1, otherwise the removing step cannot be carried out. This
contention implies that the claim does not require removal of any portions as
recited in the removing step unless a portion of the gates or oxide layer are
outside of an active area. Thus, the claim is reasonably clear. That is, if no
floating gate or block oxide layer portions “are outside of an active area,”
the removal of such portions is not required.
As such, skilled artisans would have understood the meaning and
scope of the claim as Appellant argues (App. Br. 10). Under Miyazaki,
supra, slip op. at 16, claim 1 is “sufficiently definite such that those skilled
in the art would understand what is being claimed when the claim is read in
light of the Specification.” Accordingly, we will not sustain the Examiner’s
35 U.S.C. § 112, 2nd paragraph rejection of claims 1-8.
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Prior Art Rejections
With respect to the anticipation rejection of claim 1, Appellant argues
(App. Br. 12) that “there is no disclosure of ‘. . . removing a portion of the
block oxide layer and the sidewall floating gates that are outside of an active
area of the semiconductor substrate . . .’ In fact, there is not even disclosure
of any removal of any portion of sidewall floating gates in Chang et al.”
The Examiner found (Ans. 4) that “portions of the . . . poly layer/floating
gates 210/210a are removed from elsewhere on the substrate in order to form
the structure shown in fig. 2D.”
Chang supports the Examiner’s finding. Chang discloses removing
portions of the floating gates 210a from conductor 210 in the isolation
regions – regions that by definition are outside of the active regions (FF 1,
3). (Chang’s process of producing multiple memory devices,
notwithstanding that Chang depicts only one such device in the process
flow, implies that multiple active and isolation regions are defined for each
device (see FF 2, 5)). Moreover, claim 1 only calls for removing a portion
of the gates (or block oxide layer) that are outside of an active area. Thus,
removing portions of the gates and block oxide layer from any single active
area as Chang also teaches (FF 5, see also FF 4), constitutes removing such
portions from another (i.e., “an”) active area, thereby meeting the argued
claim limitation.
Appellant’s mere denials quoted supra fail to demonstrate Examiner
error in a clear fashion. “The problem in this case is that the appellants
failed to make their intended meaning explicitly clear.” In re Morris, 127
F.3d 1048, 1056 (Fed. Cir. 1997). “It is the applicants’ burden to precisely
define the invention, not the PTO’s.” Id.
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Appellant also asserts (App. Br. 12) that Chang does not disclose
“forming sidewall spacers on sidewalls of the sidewall floating gates and the
word line . . .” Appellant explains (id.) that Figure 2D of Chang only
illustrates “spacer 220 . . . formed only on the sidewalls of floating gate
210a. However, unlike the recitations of the claims, spacer 220 is not also
formed on the sidewall of a word line.”
The Examiner (Ans. 10) points to Chang’s spacers 224 as formed on
the word line 216 (referenced by Chang as a control gate (FF 6)).
Specifically, the Examiner (Ans. 10) “pointed out [that] Chang … clearly
disclose forming sidewall spacers 224 (not 220) on the sidewalls of the
sidewall floating gates 210a and the word line 216 (fig. 2E)” and noted that
Appellant’s Brief “ignores” a similar earlier finding. Chang’s disclosure
supports the Examiner (see FF 6). Sidewall spacers 224 exist along the
sidewalls of sidewall floating gates 210a and control gate (i.e., word line)
216 (FF 6). Chang’s control gate 216 reasonably constitutes a word line
because it controls the information stored in the memory device (see FF 3).
Moreover, by failing to address the Examiner’s specific findings with
respect to the spacers 224 in Figure 2E and to explain why Chang’s control
gate 216 is distinct from the recited word line, Appellant has not met the
burden on appeal of demonstrating error. See Kahn, 441 F.3d at 985-86;
Morris, 127 F.3d at 1056.
Accordingly, we will sustain the anticipation rejection based on
Chang of claim 1, and claims 2, 5, 7 and 8 which were not separately argued
(App. Br. 12) and fall with claim 1. Appellant’s arguments (App. Br. 13-16;
Reply Br. 3-4) against the obviousness rejections of claims 3 and 4 based on
Chang, and claim 6 based on Chang and Mokhlesi, parallel the arguments
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for claim 1. Accordingly, for the reasons discussed supra with respect to
claim 1, we will also sustain the rejections of claims 3, 4 and 6. See 37
C.F.R. § 41.37(c)(1)(vii); In re Nielson, 816 F.2d 1567, 1572 (Fed. Cir.
1987).

CONCLUSION
Appellant demonstrated that the Examiner erred in finding that claim
1 is indefinite under 35 U.S.C. § 112, second paragraph. Appellant did not
show that the Examiner erred in finding that Chang teaches “removing a
portion of the block oxide layer and the sidewall floating gates that are
outside of an active area of the semiconductor substrate” and “forming
sidewall spacers on sidewalls of the sidewall floating gates and the word
line,” as set forth in claim 1.
DECISION
We affirm the Examiner's decision rejecting claims 1-8.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136. See 37 C.F.R.
§ 1.136(a)(1)(iv).

Appeal 2009-002124
Application 11/024,436

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AFFIRMED

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