Ex Parte Jones et alDownload PDFPatent Trials and Appeals BoardMay 31, 201914886818 - (D) (P.T.A.B. May. 31, 2019) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE FIRST NAMED INVENTOR 14/886,818 10/19/2015 Patrick Jones 57579 7590 06/04/2019 MURPHY, BILAK & HOMILLER/INFINEON TECHNOLOGIES 1255 Crescent Green Suite 200 CARY, NC 27518 UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. 1012-1186/2014P51725 4401 us EXAMINER GAMINO, CARLOS J ART UNIT PAPER NUMBER 1735 NOTIFICATION DATE DELIVERY MODE 06/04/2019 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): official@mbhiplaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte PA TRICK JONES, CHRISTOPH KOCH, and MICHAEL SIELAFF Appeal2018-006837 Application 14/886,818 Technology Center 1700 Before ROMULO H. DELMENDO, BEYERL YA. FRANKLIN, and CHRISTOPHER C. KENNEDY, Administrative Patent Judges. DELMENDO, Administrative Patent Judge. DECISION ON APPEAL The Applicant 1 ("Appellant") appeals under 35 U.S.C. § 134(a) from the Primary Examiner's final decision to reject claims 1-15. 2 We have jurisdiction under 35 U.S.C. § 6(b). We affirm. 1 The Applicant is "Infineon Technologies AG" (Application Data Sheet filed October 19, 2015, 5), which is also identified as the real party in interest (Appeal Brief filed March 7, 2018 ("Appeal Br."), 2). 2 Appeal Br. 3-18; Reply Brief filed June 21, 2018 ("Reply Br."), 2-9; Final Office Action entered October 3, 2017 ("Final Act."), 2-9; Examiner's Answer entered May 3, 2018 ("Ans."), 3-11. Appeal2018-006837 Application 14/886,818 I. BACKGROUND The subject matter on appeal relates to a method for soldering a circuit carrier to a carrier plate such that the circuit carrier can be connected reliably to the carrier plate within a predetermined target area (Specification filed October 19, 2015 ("Spec."), ,r 4). Figures IB and IC are illustrative and are reproduced from the Drawings filed October 19, 2015 as follows: FIG 1B Figure IB above shows a cross-section through a portion of an assembly with, inter alia, three circuit carriers 2 soldered to a common carrier plate 3 as shown in Figures IA (not reproduced) and IC along plane El-El (shown in Figure IA); and Figure 1 C shows the assembly according to Figure IA with certain components removed (for illustrative purposes) in one of the circuit carriers 2 to reveal a cutout 42 formed as a through-opening in circuit carrier 2's lower metallization layer 22 for engaging projection 41 to limit 2 Appeal2018-006837 Application 14/886,818 floating of the circuit carrier 2 during soldering (in which solder 5 is in the liquid state) of the circuit carrier 2 to the circuit plate 3 (Spec. ,r,r 8-10, 29, 30). Representative claim 1 is reproduced from the Claims Appendix to the Appeal Brief (reformatted), as follows: 1. A method for soldering a circuit carrier to a carrier plate, the method comprising: providing a carrier plate having an upper side and a first adjusting device; providing a circuit carrier having an underside and a second adjusting device; providing a solder; placing the circuit carrier onto the carrier plate in such a way that: the underside of the circuit carrier faces the upper side of the carrier plate; the solder is arranged between the carrier plate and the circuit carrier; and the first adjusting device forms a stop for the second adjusting device that limits a displacement of the circuit carrier placed on the carrier plate along the upper side of the carrier plate; and after placing the circuit carrier onto the carrier plate, melting the solder and subsequently cooling down the melted solder until it solidifies and connects the circuit carrier to the carrier plate in a material-bonding manner at a lower metallization layer of the circuit carrier. (Appeal Br. 19.) II. REJECTIONS ON APPEAL The Examiner maintains two rejections, as follows: A. Claim 15 under AIA 35 U.S.C. § 112(b) as indefinite; and B. Claims 1-15 under 35 U.S.C. § 103 as unpatentable over Ozaki 3 Appeal2018-006837 Application 14/886,818 et al. 3 in view of the Inventors' admitted prior art. (Ans. 3-11; Final Act. 2-9.) III. DISCUSSION Rejection A (Indefiniteness). Claim 15 recites: "The method of claim 1, wherein each projection is formed in the upper side of the carrier plate, and wherein each cutout is formed in the lower metallization layer of the circuit carrier" (Appeal Br. 21 ). The Examiner concludes that claim 15 is indefinite because the limitations "each projection" and "each cutout" lack proper antecedent bases (Final Act. 2). The Appellant does not comment on or contest this rejection (Appeal Br. 3-18). Because the rejection has not been contested in the Appeal Brief, we summarily affirm. Hyattv. Dudas, 551 F.3d 1307, 1314 (Fed. Cir. 2008) ("In the event of ... a waiver, the [Board] may affirm the rejection ... without considering the merits."). Rejection B (Obviousness). As a preliminary matter, we observe the Appellant's allegation that the Examiner's rejection of claim 1, as maintained in the Answer, constitutes a new ground of rejection relative to the rejection in the Final Action (Reply Br. 3--4). We do not have jurisdiction over this matter because the issue whether the Answer should have designated the rejection of claim 1 as a new ground of rejection must 3 WO 2014/069143 Al, published May 8, 2014. The Examiner and the Appellant refer to this document by the sixth-named inventor's last name, "Asai," but use Ozaki et al. ("Ozaki"; US 2015/0289375 Al, published October 8, 2015) as an English-language translation (Final Act. 3; Appeal Br. 3). To avoid confusion, we also refer to this document as "Asai" but our citations are to Ozaki, the US document. 4 Appeal2018-006837 Application 14/886,818 be raised by filing a timely petition for supervisory review pursuant to 3 7 C.F .R. § 1.181 ( as distinguished from a review of an appeal under 35 U.S.C. § I34(a)). 37 C.F.R. § 4I.40(a) ("Failure of appellant to timely file such a petition will constitute a waiver of any arguments that a rejection must be designated as a new ground of rejection."). Turning to the issues that are raised properly in the Appeal Brief, 4 all claims stand or fall with claim 1, which we select as representative, unless separately argued within the meaning of 37 C.F.R. § 4I.37(c)(l)(iv). We address claim 1 and any other separately-argued claims below. 1. Claim 1 The Examiner finds that Asai describes a method for fixing a circuit board 20 having a lower metallization layer 23 (23a in Fig. 4) ( corresponding to the Inventors' "circuit carrier") to a heat dissipation member 51, ( corresponding to the Inventors' "carrier plate") (Final Act. 3 (referring to Ozaki, Figs. IA and 4; ,r 26); see also Ans. 3--4 (explaining first circuit board 20' s layer 23a is joined to heat dissipation layer 51 via layer 23a)). The Examiner acknowledges that Asai's method differs from the method recited in claim 1 in that the prior art method does not use adjusting devices and solder to facilitate the fixing of the circuit board 20 to the heat dissipation member 51 (Final Act. 3--4 ). With respect to the adjusting devices, the Examiner finds that Asai teaches recesses 24 and projections 33 to permit determining and ensuring correct relative placement of components (id. at 4 ( citing Ozaki ,r 27) ). 4 We decline to address any issue raised in the Reply Brief that was not previously raised in the Appeal absent a showing of good cause. See 37 C.F.R. § 41.4I(b)(2). 5 Appeal2018-006837 Application 14/886,818 Based on this finding, the Examiner concludes that "[i]t would have been obvious to one of ordinary skill in the art ... to incorporate the recess and projection concept into metal layer (23) of board (20) and upper surface member (51), respectively, in order to determine/ensure the relative placement of the work components" (id. (bolding added)). With respect to the solder, the Examiner points out that Asai teaches using solder (id. at 3 (citing Ozaki ,r 26)). In addition, the Examiner finds that the Inventors' admitted prior art acknowledges that it was known to solder a carrier plate to a circuit carrier (id. at 4 ( citing Spec. ,r 3)). The Examiner concludes that "[i]t would have been obvious to one of ordinary skill in the art ... to fix the board [20] to the [heat dissipating] member [ 51] using solder since this is a known means of fixing in the art, minus any unexpected results" (id. (alterations in brackets)). The Appellant contends that no prima facie case of obviousness has been established because the "claimed invention is directed to connecting a circuit carrier to a carrier plate without intermediary connectors," whereas "Asai discloses electrically connecting a first circuit board 20 to a second circuit board 40 using corresponding male and female connectors 30, 43" (Appeal Br. 4 (some bolding added)). According to the Appellant, the Examiner "equates one of the recesses 24 formed in the upper surface of Asai's first circuit board 20 to [the] Appellant's claimed first adjusting device, and the corresponding projection 33 located on the lower surface of Asai's male connector 30 to [the] Appellant's claimed second adjusting device" (id. at 4--5). In the Appellant's view, the Examiner "has arbitrarily drawn boundaries in a structure where these boundaries serve no other purpose than to meet the limitations of the claims" (id. at 5). In addition, the 6 Appeal2018-006837 Application 14/886,818 Appellant urges that the Examiner failed to provide a sufficient articulated reasoning to modify Asai in the manner claimed by the Inventors as the Examiner fails to explain why the structure taught by Asai is inadequate and, therefore, in need of modification (id. at 8). The Appellant argues that "Asai is clearly directed to a connector-based circuit board connection technique and not a direct board-to-board connection approach" and that "there is no teaching or suggestion in Asai for such a direct board-to-board connection approach" (id. at 9). Furthermore, the Appellant urges that the Examiner mischaracterizes paragraph 3 of the Specification as admitted prior art (id. at 11-12). The Appellant's arguments fail to identify any reversible error in the Examiner's rejection. In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011). As the Examiner points out (Ans. 3--4), the Appellant's arguments reveal that the Appellant misread ( and consequently misunderstood) the rejection of claim 1 as set forth in the Final Action. The rejection in the Final Action provides sufficient notice that the Examiner is relying on connecting Asai's circuit board 20, which corresponds to the Inventors' "circuit carrier," to the upper surface of heat dissipation member 51, which corresponds to the Inventors' "carrier plate" via metal layer 23 (Ozaki Figs. 1 and 4), which is indicated in Asai's Figure 4 as second metal layer 23a (Final Act. 3--4). Cf Chester v. Miller, 906 F.2d 1574, 1578 (Fed. Cir. 1990) ("[35 U.S.C. §] 132 is violated when a rejection is so uninformative that it prevents the applicant from recognizing and seeking to counter the grounds for rejection."). Thus, even if we accept the Appellant's conclusory claim construction that the "claimed invention is directed to connecting a circuit carrier to a 7 Appeal2018-006837 Application 14/886,818 carrier plate without intermediary connectors" (Appeal Br. 4 ( emphasis removed)), many of the Appellant's arguments focusing on Asai's connectors 30 and 43 are inconsequential or irrelevant to the basic thrust of the Examiner's rejection-i.e., that a person having ordinary skill in the art would have found it obvious to modify Asai' s method by implementing the techniques of using adjusting devices and solder to fix circuit board 20 to heat dissipation layer 51 via metal layer 23 ( or 23a). Specifically, Asai's Figure 4 (annotated) is reproduced as follows: Fig.4 (cerrier plate} Asai' s Figure 4 above depicts, inter alia, a first circuit board 20 and a second circuit board 40 fixed to two heat dissipation members 51, respectively (Ozaki ,r 42). In this regard, the Appellant does not dispute the Examiner's findings that Asai' s first circuit board 20 and the lower heat dissipation member 51 may properly be considered as the Inventors' "circuit carrier" and "carrier plate" as recited in claim 1, respectively (Appeal Br. 4-- 12). Although Asai does not specifically disclose the technique(s) used to fix second metal layer 23a to the lower heat dissipation member 51, Asai shows that it was known to use (1) a recesses 24-projections 33 system and 8 Appeal2018-006837 Application 14/886,818 (2) an adhesive such as solder to facilitate fixing and adhering of two workpieces or electronic components (Ozaki ,r,r 26-27, 41--42). Thus, we discern no reversible error in the Examiner's conclusion that a person having ordinary skill in the art would have been prompted to implement-through no more than ordinary creativity-the known techniques of using a recesses- projections system and solder to assist in fixing and adhering Asai's first circuit board 20 to the lower heat dissipation member 51 via the second metal layer 23 (or 23a). KSR Int'! Co. v. Teleflex Inc., 550 U.S. 398,417 (2007) ("[I]f a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill."). We find no persuasive merit in the Appellant's procedural argument that the "Background" section (Spec. ,r 3) has not been shown to be a prior art admission (Appeal Br. 11-12). That section states that "[c]ircuit carriers are usually soldered to the carrier plate" (Spec. ,r 3, first sentence (emphasis added)). Although the Appellant is correct this does not admit explicitly that the information is prior art, a reasonable inference may be drawn from the use of the term "usually" that the use of solder to fix a circuit carrier to a carrier plate was known in the prior art. As the Examiner states (Ans. 7), despite the knowledge in the Appellant's possession on whether the information is prior art or the Inventors' own work or discovery, it fails to confirm the prior art status of the information. Instead, the Appellant argues only that the Examiner has not proven that the information is prior art. Consistent with the Examiner well-reasoned position (Ans. 7), we find the statement that the "Appellant does not doubt there exists a host of references 9 Appeal2018-006837 Application 14/886,818 that show soldering a carrier plate to a circuit carrier" (Appeal Br. 12) to be a tacit admission that the information was known in the prior art. 5 In any event, a conclusion of obviousness in this case does not require the use of the Background section information as admitted prior art because, as the Examiner finds (Final Act. 4 ("solder ... is a known means of fixing in the art")), the use of solder to join electric components is well known as evidenced by Asai (Ozaki ,r,r 26, 41). For these reasons, and those well-stated by the Examiner, we uphold the Examiner's rejection of claim 1. 2. Claims 10---12 The Appellant provides a skeletal argument that the rejection contains a statement that is "conclusory and self-serving" (Appeal Br. 13 (emphasis removed)). According to the Appellant, the Final Action "fails to provide any explanation as to why the specific arrangement of features recited in claims 10-12 would have been obvious over the teachings of just Asai" (id.). We disagree. The Appellant fails to explain why the Appellant believes that Asai' s method, as modified in the manner as suggested for claim 1 (Ans. 7), would lack the limitations recited in claims 10-12. A person having ordinary skill in the art would have understood that recesses can be provided in either of Asai' s lower metal layer 23a or the heat dissipating member 51; similarly, a person having ordinary skill in the art would have understood that projections could be provided on either Asai's 5 To the extent that the Inventors, the Appellant, or anyone involved in the filing and prosecution of the application is/are aware that such information is prior art, that fact establishing its prior art status must be disclosed to the PTO under the duty of candor and good faith regardless whether the Examiner properly requested or required that information. 10 Appeal2018-006837 Application 14/886,818 lower metal layer 23a or the heat dissipating member 51. When recesses are provided on metal layer 23a, the limitations recited in claims 10-12 would appear to be met. 3. Claim 15 Claim 15, which depends from claim 1, recites "wherein each projection is formed in the upper side of the carrier plate, and wherein each cutout is formed in the lower metallization layer of the circuit carrier" (Appeal Br. 21 ). The Appellant's argument for claim 15 is similar to that provided for claims 10-12 in that it is skeletal. Therefore, we do not find the argument persuasive for the same or similar reasons as provided for claims 1 and 10- 12. 4. Claims 5 and 6 Because the Appellant does not argue claim 5 separately from claim 6, we limit our discussion to claim 5, which recites: 5. The method of claim 1, wherein the first adjusting device forms a stop for the second adjusting device that allows a linear displacement of the circuit carrier placed on the carrier plate in any direction parallel to the underside of the circuit carrier with a play of at least 0.1 mm and/or a play limited to a maximum of 0.4 mm. (Appeal Br. 20.) The Appellant argues that the Examiner failed to provide some articulated reasoning in reaching a conclusion of obviousness as to these claims (Appeal Br. 15-16). That is incorrect because the rejection includes some articulated reasoning with some rational underpinning, and the Appellant fails to identify any reversible error in that reasoning. 11 Appeal2018-006837 Application 14/886,818 Specifically, a person having ordinary skill in the art would have drawn a reasonable inference from Asai' s teachings that the described recesses and projections, when engaged, are designed to limit relative movement of the components provided with such recesses and projections. (Ozaki Figs. IA, 4; ,r,r 27, 42). Therefore, their dimensions and sizes would have been understood to be result-effective variables. In re Preda, 401 F.2d 825, 826 (CCP A 1968) ("[I]n considering the disclosure of a reference, it is proper to take into account not only specific teachings of the reference but also the inferences which one skilled in the art would reasonably be expected to draw therefrom."); In re Applied Materials, Inc., 692 F.3d 1289, 1296 (Fed. Cir. 2012) ("The Board also found that a person of ordinary skill in the art would have recognized that changing the groove width would affect the polishing rate and uniformity. This is a reasonable conclusion because the number of grooves per area ... is related to the groove width."). Based on the foregoing, we conclude that the determination of optimum or workable dimensions and sizes for the recesses and projections to achieve limited movement would have been obvious as a matter of routine experimentation. In re Aller, 220 F.2d 454, 456 (CCPA 1955) ("[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation."). Accordingly, we sustain the rejection of claims 5 and 6. 5. Claim 9 Claim 9, which depends from claim 1 through intervening claim 8, recites that "the dielectric insulation carrier is a ceramic platelet" (Appeal Br. 21). 12 Appeal2018-006837 Application 14/886,818 The Examiner finds that "it is well-known to use ceramic dielectric materials as the insulating layer due to the electrical insulating properties of ceramics" (Final Act. 7 (emphasis removed)). The Appellant argues that the Examiner failed to provide some articulated reasoning (Appeal Br. 16). We disagree with the Appellant. As indicated above, the Examiner did articulate some reasoning, and that reasoning has not been shown to include any reversible error. Indeed, the Appellant acknowledges that "it may be true that ceramic dielectric materials may be used as the insulating layer due to the electrical insulating properties of ceramics" but argues only that "Asai itself provides no rationale for substituting its insulating substrate 21 with a ceramic platelet" (id.). But that argument ignores the instructions given by the Supreme Court of the United States in analyzing obviousness, and, therefore, fails. KSR, 550 U.S. at 419 ("The obviousness analysis cannot be confined by a formalistic conception of the words teaching, suggestion, and motivation, or by overemphasis on the importance of published articles and the explicit content of issued patents."). Therefore, we sustain the rejection of claim 9. 6. Claim 4 Claim 4, which depends from claim 1, recites in relevant part: "wherein the first adjusting device forms a stop for the second adjusting device that limits a displacement of the circuit carrier placed on the carrier plate in a direction along the upper side of the carrier plate and/or limits a rotation of the circuit carrier placed on the carrier plate" (Appeal Br. 19-20). The Appellant contends that "the mere fact that a projection can fit into a recess does not automatically indicate either that the projection forms a stop of the recess, or that the projection limits the displacement of first 13 Appeal2018-006837 Application 14/886,818 circuit board 20" (id. at 17). For the reasons given by the Examiner (Ans. 9- 10), we disagree with the Appellant. As the Examiner points out, when Asai's projections are inserted into the recesses, a person skilled in the art would understand from simple observation and common sense that the "projection would limit the movement of the circuit board (20) in the x and y directions" (id. at 10; Ozaki Fig. 4). See, e.g., In re Bozek, 416 F.2d 1385, 1390 (CCPA 1969). Therefore, we sustain the rejection of claim 4. 7. Claim 14 Claim 14 recites: "The method of claim 1, wherein the circuit carrier has an upper side populated with a semiconductor chip" (Appeal Br. 21 ). In the Final Action, the Examiner finds that Asai' s male connector is a chip (Final Act. 7). The Appellant argues that "Asai's male connector 30 are [sic] disclosed to represent a male connector that fits into female connector 43, and nothing more" (Appeal Br. 17). In response, the Examiner adds that Asai's modules 10 and 11 (Ozaki Figs. IA and 4) are also semiconductor chips (Ans. 10). In the Reply Brief, the Appellant offers a dictionary definition for "semiconductor chip" (i.e., an integrated circuit that combines multiple transistors and other components on a single piece of semiconductor material) but does not otherwise comment on the Examiner's finding regarding Asai's modules 10 and 11 (Reply Br. 8-9). We concur with the Examiner. Asai's modules 10 and 11 include circuit boards 20 and/or 40, which are known to include semiconductor chips (Figs. IA and 4). Therefore, we sustain the rejection of claim 14. 14 Appeal2018-006837 Application 14/886,818 IV. SUMMARY Rejections A and Bare sustained. Therefore, the Examiner's final decision to reject claims 1-15 is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). AFFIRMED 15 Copy with citationCopy as parenthetical citation