Ex Parte Jones

Patent Trial and Appeal Board

Jun 26, 2017

13686588 (P.T.A.B. Jun. 26, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/686,588 11/27/2012 William Evan Jones III 1458-120226 4561
109712 7590 06/28/2017
Advanced Micro Devices, Inc.
c/o Davidson Sheehan LLP
8834 North Capital of TX Hwy
Suite 100
Austin, TX 78759
EXAMINER
ELMORE, REBA I
ART UNIT PAPER NUMBER
2131
NOTIFICATION DATE DELIVERY MODE
06/28/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing@ds-patent.com
AMD@DS-patent.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte WILLIAM EVAN JONES, III
(Applicant: Advanced Micro Devices, Inc.)
Appeal 2017-001742
Application 13/686,588
Technology Center 2100
Before ERIC B. CHEN, IRVIN E. BRANCH, and
KARA L. SZPONDOWSKI, Administrative Patent Judges.
BRANCH, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134 from a rejection of claims 1—
25. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part.
Appeal 2017-001742
Application 13/686,588
CLAIMED SUBJECT MATTER
The claims are directed to preventing multiple processors from taking
ownership of shared memory locations. See Spec. Abstract.
Claim 1, reproduced below, is illustrative of the claimed subject
matter:
1. A method comprising:
maintaining a set of memory addresses at a buffer
responsive to memory access requests generated by a processor
core;
receiving, at the processor core, a probe indicating a
request to access a memory location associated with a memory
address; and
blocking the probe responsive to the memory address
being stored at the buffer.
REFERENCE AND REJECTION
Claims 1—25 stand rejected under pre-AIA 35 U.S.C. § 103(a) as
unpatentable over Saha (US 2006/0004998 Al, published Jan. 5, 2006).
Ans. 3-12.
CONTENTIONS
Appellant argues the Examiner erred in rejecting claim 1 because
Saha does not disclose “blocking the probe responsive to the memory
address being stored at the buffer.” App. Br. 3—6; Reply Br. 2—3.
Appellant also argues the Examiner erred in rejecting claim 5 because
Saha does not disclose “discarding the transaction from the queue in
response to receiving the data; and maintaining the memory address at the
buffer after discarding the transaction from the queue.” App. Br. 7; Reply
Br. 4-5.
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Appeal 2017-001742
Application 13/686,588
Appellant also argues the Examiner erred in rejecting claim 6 because
Saha does not disclose “discarding the memory address from the buffer in
response to expiration of a timer.” App. Br. 7—8; Reply Br. 5.
ANALYSIS
Regarding claim 1, the Examiner finds
[Saha’s] monitor logic and the cache coherency logic are both
based on requested data being at an address which is determined
to be or not be in a buffer or cache. The monitor logic and cache
coherency logic both use comparisons of addresses to determine
whether or not a particular address is or might be in the buffer or
cached. Both are activities which are monitored or snooped in a
multiple processor system and both activities require knowing
the address in memory for the data or instructions in either a
buffer or a cache. Paragraph 0019 also discusses using monitor
logic to determine whether or not a memory location will be in
contention.
Ans. 13—14 (citing Saha ^fl[ 18, 19 (a processor “may assert a signal or
employ some procedure that prevents any other thread (or processor) from
accessing the memory location in question”)).
Appellant does not dispute that Saha discloses a procedure for
blocking access to a particular memory location and does not persuasively
rebut the Examiner’s reasoning that “[t]he monitor logic and cache
coherency logic both use comparisons of addresses to determine whether or
not a particular address is or might be in the buffer or cached[, which]
require knowing the address in memory for the data or instructions in either
a buffer or a cache.” Ans. 13—14. See, generally, Reply Br. 2—3.
Accordingly, we are unpersuaded of error in the Examiner’s reasoning that,
in order to block an attempted access to an in-use memory location, the
address of the memory location must be stored somewhere so that a
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Appeal 2017-001742
Application 13/686,588
comparison can be made. Ans. 13. Because the blocking is then a result of
that comparison, Saha at least suggests “blocking the probe responsive to the
memory address being stored at the buffer.” Saha Tflf 18—19. Notably,
claim 1 does not require any particular “buffer,” other than one that
maintains addresses “responsive to memory access requests generated by a
processor core,” which Saha discloses. Id. 119.
Accordingly, we sustain the Examiner’s decision to reject claim 1.
Claim 5 depends from claims 4, 3, and 1 and recites “discarding the
transaction from the queue in response to receiving the data; and maintaining
the memory address at the buffer after discarding the transaction from the
queue.” We do not sustain the Examiner’s decision to reject claim 5. In
particular, we do not find the Examiner adequately explained how Saha
discloses that the memory address is maintained after the transaction is
discarded. See generally Ans. 5, 16—17.
Claim 6 depends from claims 3 and 1 and recites “discarding the
memory address from the buffer in response to expiration of a timer.”
Appellant argues claim 6 on the basis that Saha fails to disclose a timer “in
any manner.” App. Br. 7—8. We disagree because, as the Examiner finds
(Ans. 6), “processing systems and memory systems operate upon using the
highs and lows of clock signals for starting and ending operations,” which is
a form of a timer.
Accordingly, we sustain the Examiner’s decision to reject claim 6.
Appellant argues claims 2—\ and 7—25 on the same basis as claim 1.
App. Br. 8—9. Accordingly, we sustain the Examiner’s decision to reject
claims 2-4 and 6—25 for the foregoing reasons.
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Appeal 2017-001742
Application 13/686,588
DECISION
We affirm the Examiner’s decision to reject claims 1—4 and 6—25. We
reverse the Examiner’s decision to reject claim 5.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(l)(iv).
AFFIRMED-IN-PART
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