Ex Parte Johnson

Board of Patent Appeals and Interferences

Aug 5, 2008

11210290 (B.P.A.I. Aug. 5, 2008)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
_____________

Ex parte GARY M. JOHNSON
_____________

Appeal 2008-2513
Application 11/210,290
Technology Center 2800
______________

Decided: August 5, 2008
_______________

Before KENNETH W. HAIRSTON, ROBERT E. NAPPI,
and SCOTT R. BOALICK, Administrative Patent Judges.

NAPPI, Administrative Patent Judge.

DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 6(b) of the final
rejection of claims 11, 16 through 18, 23, 24, 45, and 491.
We affirm the Examiner’s rejections of these claims.

1 The Examiner withdrew the rejections of claims 12 through 15, 19 through
22, 46 through 48, 50 and 51. See pages 2 and 3 of the Answer. Claims 1
through 10, and 25 through 44 have been cancelled.
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INVENTION
The invention is directed towards a device to perform switching of
capacitance in a Delayed Locked Loop (DLL). See page 5 of Appellant’s
Specification. Claim 11 is representative of the invention and reproduced
below:
11. A delay lock loop to provide an output signal based upon a phase
difference between a reference signal and a feedback signal,
comprising:
a coarse delay unit to provide said coarse delay upon at least one of
said reference signal and a data output signal;
a fine delay unit for switching an activation of a capacitive delay to
provide a fine tuned delay upon at least one of said reference
signal and said data output signal;
a phase detector to detect said phase difference; and
a feedback delay unit to provide a delay upon said output signal to
generate said feedback signal.

REFERENCES
Taniguchi US 6,242,954 B1 Jun. 5, 2001
Bhullar US 6,683,982 B2 Jan. 27, 2004
(filed Oct. 3, 2001)

REJECTION AT ISSUE
Claims 11, 16 through 18, 23, 24, 45, and 49 stand rejected under 35
U.S.C. § 103(a) as being unpatentable over Bhullar in view of Taniguchi.
The Examiner’s rejection is on pages 3 and 4 of the Answer.
Throughout the opinion, we make reference to the Brief (received
February 2, 2007), Reply Brief (received September 4, 2007) and the
Answer (mailed July 2, 2007) for the respective details thereof.
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ISSUES
Appellant argues on pages 8 and 12 of the Brief that the Examiner’s
rejection of claims 11, 16 through 18, 23, 24, 45, and 49 is in error.
Appellant asserts that the Examiner has not established that one skilled in
the art would be motivated to combine Bhullar and Taniguchi. App. Br. 9,
10. Appellant asserts that the Appellant’s Specification teaches away from
systems such as Bhullar’s and that the Examiner’s rejection relies upon
hindsight reasoning. App. Br. 10, 11. Further, Appellant asserts that even if
the references were properly combined the combination does not teach
switching an activation of a capacitive delay as claimed. App. Br. 10.
Thus, Appellant’s contentions with respect to the rejection of claims
11, 16 through 18, 23, 24, 45, and 49 present us with two issues; whether the
Examiner erred in combining Bhullar and Taniguchi and whether the
Examiner erred in finding that the combination of the references teach
switching an activation of a capacitive delay as claimed.

PRINCIPLES OF LAW

On the issue of obviousness, the Supreme Court has recently stated
that “the obviousness analysis cannot be confined by a formalistic
conception of the words teaching, suggestion, and motivation.” KSR Int’l
Co. v. Teleflex Inc., 127 S. Ct. 1727, 1741 (2007). Further, the Court stated
“[t]he combination of familiar elements according to known methods is
likely to be obvious when it does no more than yield predictable results.”
KSR Int’l Co. v. Teleflex Inc., 127 S. Ct. 1727, 1739 (2007).
When a work is available in one field of endeavor, design
incentives and other market forces can prompt variations of it,
either in the same field or a different one. If a person of
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ordinary skill can implement a predictable variation, § 103
likely bars its patentability. For the same reason, if a technique
has been used to improve one device, and a person of ordinary
skill in the art would recognize that it would improve similar
devices in the same way, using the technique is obvious unless
its actual application is beyond his or her skill. . . . [A] court
must ask whether the improvement is more than the predictable
use of prior art elements according to their established
functions.

Id. at 1740. “One of the ways in which a patent’s subject matter can be
proved obvious is by noting that there existed at the time of the invention a
known problem for which there was an obvious solution encompassed by the
patent’s claims.” Id. at 1742.

FINDINGS OF FACT
1. Bhullar teaches a switched delay compensation for a Delay Locked
Loop (DLL). Abstract.
2. Bhullar teaches that the DLL adjusts delay in steps. There are coarse
delay adjustment elements and fine delay adjustment elements. The
selection of individual elements allow the delay of the loop to be
adjusted. Col. 1, ll. 24-36, col. 3, ll. 18-25.
3. The individual coarse delay elements consist of a resistor-capacitor
and an inverter which are selected by a multiplexer. The fine delay
elements include binary capacitors which are selectable by an
decoder. Bhullar, col. 4, ll. 34-42, and figure 2.

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4. Bhullar discusses the selection of delay elements as switching but
does not describe the circuit or mechanism which actually inserts the
delay element into the delay loop. Rather, Bhullar states that such
details are “well understood by persons skilled in the art.” Col. 4, ll.
63-67.
5. Taniguchi teaches a hierarchal DLL circuit which includes coarse and
fine delay adjustments. Abstract.
6. Taniguchi teaches that the fine delay circuit element capacitors are
inserted into the delay loop by transistors (switches TR1-32). Fig 9,
col. 10, ll. 9-19.

ANALYSIS
Initially, we note that Appellant’s Brief identifies each independent
claim rejected, on page 12 of the Brief. However, these statements
associated with each claim merely recite the limitations of the claim and
state that they are not taught. Such statements are not separate arguments
under 37 C.F.R. § 41.37 (c)(1)(vii). As such Appellant has grouped all of
the rejected claims together.
Appellant’s arguments have not persuaded us that the Examiner erred
in combining Bhullar and Taniguchi. We find that both references teach a
delay lock loop circuit which has fine delay elements that include capacitors.
Facts 3, 6. We find that both references teach that the elements are selected
to create the desired delay. Facts 2, 5. Bhullar teaches that the method of
connecting the elements to the delay loop (activating the delay element) is
within the level of ordinary skill in the art. Fact 4. Taniguchi teaches that
one method of connecting the fine elements into the circuit involves the use
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of transistors which switch the elements into the delay loop. Fact 6. Thus,
Taniguchi teaches that it was within the level of ordinary skill in the art to
use transistors to switch capacitive elements into a delay loop. We consider
the use of transistors as switches to connect the fine delay elements
(capacitors) into the circuit to represent nothing more than using a known
circuit for its known purpose.
Appellant’s assertion, on page 10 of the Brief, that Appellant’s
Specification teaches away from systems such as Bhullar’s which use
multiplexers, has not persuaded us of error in the Examiner’s rejection.
Initially, we note that Appellant has not identified any teaching in Bhullar
which allegedly teaches away from the modification. Further, we note that
Bhullar does not teach using multiplexers to select the fine delay loop
elements, rather, Bhullar teaches using a decoder which provides an
indication of which delay elements should be connected. Fact 3. Similarly,
Appellant’s argument that the Examiner’s combination is based upon
hindsight reasoning is not persuasive of error. As discussed supra, we
consider the combination to represent nothing more than using a known
circuit element for its known purpose. Thus, Appellant has not persuaded us
that the Examiner erred in combining the references.
Appellant’s arguments have not persuaded us that the Examiner erred
in determining that the combination of the references teaches switching an
activation of a capacitive delay as claimed. Claim 11, recites “a fine delay
unit for switching an activation of capacitive delay to provide a fine tuned
delay.” Thus, the scope of claim 11 includes that the fine delay unit
performs the function of switching and activating capacitive delay. The
Examiner has found that Bhullar teaches a fine delay unit which makes use
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of capacitors. Ans. 3. Further, the Examiner finds that Bhullar does not
disclose switches which activate the capacitive elements, but does find that
Taniguchi teaches that capacitive fine delay elements are actuated by
switches. Ans. 3, 4. We concur with the Examiner’s findings, as we find
that they are supported by ample evidence of record. Facts 3 through 6. As
discussed supra, we consider using the switches discussed by Taniguchi in
Bhullar’s DLL to be obvious. Appellant’s argument, on pages 9 and 10 of
the Brief, that “Taniguchi merely discloses connecting a capacitor, wherein
claim 11 of the present invention calls for switching an activation of the
capacitive delay” appears to draw a distinction between connecting a
capacitor and activating a capacitor.2 However, in the context of the
Taniguchi’s circuit we see no such distinction. Appellant’s Specification, on
page 15, discusses the step activating as a step by which additional
capacitance is added to the loop. In Taniguchi’s device, by connecting the
capacitor, the capacitor is put into the delay circuit and as such activated,
similarly disconnecting the capacitor would de-activate it. Thus, Appellant
has not convinced us that the Examiner erred in finding that the combination
of the references teaches “a fine delay unit for switching an activation of
capacitive delay to provide a fine tuned delay.”
For the aforementioned reasons, Appellant has not shown that the
Examiner erred in rejecting claim 11. Thus, we sustain the Examiner’s
rejection of claims 11, 16 through 18, 23, 24, 45, and 49 under 35 U.S.C.
§ 103(a) as being unpatentable over Bhullar in view of Taniguchi.

2 Appellant presents a similar argument on pages 3 and 4 of the Reply Brief.
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ORDER
The decision of the Examiner is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

KIS

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