Ex Parte Jibry

Patent Trial and Appeal Board

Dec 23, 2016

13456574 (P.T.A.B. Dec. 23, 2016)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/456,574 04/26/2012 Rafel Jibry 82961958 9901
56436 7590 12/28/2016
Hewlett Packard Enterprise
3404 E. Harmony Road
Mail Stop 79
Fort Collins, CO 80528
EXAMINER
O NEILL, PATRICK
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
12/28/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
hpe.ip.mail@hpe.com
chris. mania @ hpe. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte RAFEL JIBRY
Appeal 2015-004239
Application 13/456,574
Technology Center 2800
Before ROMULO H. DELMENDO, JAMES C. HOUSEL, and
LILAN REN, Administrative Patent Judges.
DELMENDO, Administrative Patent Judge.
DECISION ON APPEAL
The Applicant (hereinafter the “Appellant”)1 appeals under 35 U.S.C.
§ 134(a) from a final decision of the Primary Examiner to reject claims 1, 2,
4—9, and 12—20.2 We have jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part.
1 The Appellant states that the real party in interest is “Hewlett-Packard
Development Co., LP,” which is said to be “a wholly-owned affiliate of
Hewlett-Packard Company” (Appeal Brief filed, hereinafter “Appeal Br.,”
2).
2 Appeal Br. 2, 4—17; Final Office Action delivered electronically on May
16, 2014, hereinafter “Final Act.,” 2—7; Examiner’s Answer delivered
electronically on December 24, 2014, hereinafter “Ans.,” 2—13.
Appeal 2015-004239
Application 13/456,574
BACKGROUND
The subject matter on appeal relates to a signal processing device
utilizing multiple channel phase detection (Specification, hereinafter
“Spec.,” 115). According to the Appellant, “[tjhrough use of methods and
systems embodying principles described [in the Appellant’s disclosure], a
more effective and efficient manner of processing data signals is realized”
(id. 117).
Representative claim 1 is reproduced from page 19 of the Appeal
Brief (Claims Appendix), with key disputed limitations highlighted in
italicized text, as follows:
1. A signal processing device to utilize multiple
channel phase detection, the device comprising:
a first phase detector for a first Phase Locked Loop
(PLL) of a first channel, said first phase detector to generate
phase error information from an input of said first channel; and
a second phase detector of a second PLL of a second
channel, said second phase detector to generate phase error
information from an input of said second channel;
wherein, both said first PLL and said second PLL are to
receive phase error information from both said first phase
detector and said second phase detector.
REJECTIONS ON APPEAL
The Examiner rejected the claims as follows:
I. Claims 1, 2, 4, 6, 8, 9, 12, 13, and 15—20 under 35 U.S.C.
§ 102(b) as anticipated by Feller (US 7,860,190 B2,
issued December 28, 2010);
II. Claim 5 under 35 U.S.C. § 103(a) as unpatentable over
Feller; and
III. Claims 7 and 14 under 35 U.S.C. § 103(a) as
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Application 13/456,574
unpatentable over Feller in view of Chen et al. (US
8,258,890 B2, issued September 4, 2012; hereinafter
“Chen”).
(Final Act. 2—9; Ans. 2—13.)
DISCUSSION
I
With respect to Rejection I, the Appellant provides arguments under
separate headings for each of claims 1, 2, 8, 9, and 15. We address these
claims separately to the extent that they have been argued separately within
the meaning of 37 C.F.R. § 41.37(c)(l)(iv). By this rule, all claims not
separately argued stand or fall with a representative claim of our choosing,
namely claim 1.
A. Claim 1
The Examiner found that Feller describes every limitation recited in
claim 1 (Final Act. 2—3) (citing Feller, Fig. 1A; col. 3,11. 28—31; col. 4,11.
25—39). These findings were repeated in the Answer (Ans. 2—3).
The Appellant contends that the Examiner’s anticipation finding is
erroneous because Feller does not describe the limitation “both said first
PLL and said second PLL are to receive phase error information from both
said first phase detector and said second phase detector” (Appeal Br. 9).
Specifically, the Appellant argues that, in Feller, “the information is a
processed summation representing a global phase error value, received from
an intermediate device such as the global rate integrator” (id.) (citing Feller,
col. 4,11. 34—36).
We discern no reversible error in the Examiner’s anticipation finding.
In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011).
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“[DJuring patent prosecution when claims can be amended,
ambiguities should be recognized, scope and breadth of language explored,
and clarification imposed.” In re Zletz, 893 F.2d 319, 321 (Fed. Cir. 1989).
“Only in this way can uncertainties of claim scope be removed, as much as
possible, during the administrative process.” Id. at 322. “[A]s applicants
may amend claims to narrow their scope, a broad construction during
prosecution creates no unfairness to the applicant or patentee.” In re ICON
Health and Fitness, Inc., 496 F.3d 1374, 1379 (Fed. Cir. 2007).
Applying these principles, we are in complete agreement with the
Examiner’s analysis. As pointed out by the Examiner (Ans. 8), “[t]he claim
is completely silent as to whether the first and second PLL are to receive
phase error information directly or indirectly from the first and second phase
detectors” and, therefore, the claim is generic to both. Nothing in either the
claim or the remainder of the Specification requires that the first PLL and
the second PLL must receive phase error information directly from the first
phase detector and the second phase detector, as the Appellant seems to
believe. Moreover, as the Examiner aptly points out {id.), the Appellant’s
own disclosure informs one skilled in the relevant art that the disputed claim
language reads on embodiments where an intermediate component in the
form of a “global collating element” is present in the device—i.e., the phase
error information is received from the first phase detector and the second
phase detector in an indirect manner through the global collating element
(Spec. 11, claim 3 as originally filed; Fig. 3). Under these circumstances,
we construe the disputed limitations to read on embodiments in which the
first PLL and the second PLL receive phase error information indirectly
from the first phase detector and the second phase detector. Cf. Phillips v.
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Application 13/456,574
AWH Corp., 415 F.3d 1303, 1315 (Fed. Cir. 2005) (explaining that the
patent’s disclosure is the single best guide to determining the meaning of
disputed claim terms).
Under the correct claim construction, the Examiner correctly found
that Feller anticipates. Although the Appellant is correct that Feller’s system
includes a global rate integrator 32 (Figure 1 A; col. 4,11. 24—37), claim 1
does not preclude such an integrator, as we discussed above.
For these reasons, we uphold the Examiner’s rejection of claim 1.
B. Claim 2
Claim 2 recites: “The device of claim 1, wherein said first PLL is to
collate information from said first phase detector and said second phase
detector” (Appeal Br. 19).
The Examiner found that Feller anctipates claim 2 (Final Act. 3; Ans.
3).
In addition to the argument offered in support of claim 1, which we
found unpersuasive, the Appellant argues that “Feller does not even teach or
suggest each PLL receiving phase error information from multiple phase
detectors” and, therefore, fails to teach or suggest the further limitations of
claim 2 (Appeal Br. 10). According to the Appellant, “Feller teaches any
processing of the information is done, not at the circuits (1-N), but at a
distinct and intermediate element, the global rate integrator” {id. at 10-11).
Furthermore, the Appellant argues that Feller discloses summing, taking a
percent, and integrating—not collating information (id. at 11).
Again, we find no reversible error in the Examiner’s anticipation
finding for claim 2. As pointed out by the Examiner (Ans. 8—9), Feller
teaches that a “global phase error value is developed from phase error values
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Application 13/456,574
of each circuit (1, N) [i.e., PLL]” (col. 4,11. 26—28) (emphasis added). In
addition, the Examiner is also correct in finding (Ans. 9) that Feller teaches
adder 48, which sums the global phase error value with respect to local
filtered phase error values from circuits (1, N), as part of the first PLL (col.
4,11. 28—33; Fig. 1 A). Regarding the term “collate” recited in claim 2, the
Appellant does not direct us to any disclosure in the Specification or any
documentary evidence that the term excludes summation of the values from
the circuits as disclosed in Feller. Indeed, the normal meaning of “collate”
includes “to collect, compare carefully in order to verify, and often to
integrate or arrange in order.” See https://www.merriam-
webster.com/dictionary/collate. That ordinary usage supports the Examiner’s
finding (Ans. 9) that Feller teaches collating as required by claim 2.
C. Claim 8
Claim 8 recites (Appeal Br. 20) (emphases added):
8. A method for utilizing multiple channel phase
detection, the method comprising:
with a first Phase Locked Loop (PLL) of a first channel,
receiving phase error information for said first channel from a
first phase detector and phase error information for a second
channel from a second phase detector at different intervals', and
with a second PLL of said second channel, receiving
phase error information from said second phase detector and
said first phase detector at different intervals.
The Appellant argues, inter alia, that Feller does not disclose or
suggest receiving phase error information at different intervals, as required
by the claim, but rather a summed value at a single point in time (Appeal Br.
11—12). The Examiner responds that Feller’s column 1, lines 46-48
describes the disputed limitations.
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Application 13/456,574
We agree with the Appellant on this issue. Feller’s disclosure at
column 1, lines 46-48 merely states that “when severe noise and dropouts
(loss of data signal) at an individual data channel occur, that channel may
rely on the global timing error information.” We do not find that disclosure
to be sufficient to support the Examiner’s anticipation finding.
Accordingly, we cannot uphold the rejection of claim 8 (and claims 9—
14 dependent thereon).
D. Claim 15
Claim 15 recites (Appeal Br. 20):
15. A multiple channel phase detection system
comprising:
a number of channels that are nominally operating at a
same frequency, each channel comprising:
a phase detector; and
a Phase Locked Loop (PLL);
wherein each PLL for each of said channels is to receive
phase error information for its respective channel and phase
error information from at least one phase detector of a separate
channel.
In addition to the argument presented for claim 1, which we found
unpersuasive above, the Appellant argues that the Examiner’s reliance on
elements 1 -N as disclosing both the channel and PLL limitations is improper
{id. at 13). We disagree with the Appellant for the reasons given by the
Examiner (Ans. 12).
Accordingly, we uphold the rejection of claim 15.
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II & III
The Appellant relies primarily on the argument in support of claim 1,
adding that the modifications proposed by the Examiner do not cure the
deficiency with respect to claim 1 (Appeal Br. 15—17). Therefore, we affirm
Rejections II and III (as to claim 7 only) for the same reasons we upheld the
rejection of claim 1.
SUMMARY
The Examiner’s final decision to reject is affirmed as to claims 1, 2,
4—7, and 15—20 but reversed as to claims 8, 9, and 12—14.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1).
AFFIRMED-IN PART
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