Ex Parte Jiang et al

Patent Trial and Appeal Board

Mar 14, 2017

13570612 (P.T.A.B. Mar. 14, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
21545-254001 9029
EXAMINER
TALBOT, BRIAN K
ART UNIT PAPER NUMBER
1715
NOTIFICATION DATE DELIVERY MODE
13/570,612 08/09/2012
75589 7590 03/16/2017
Matheson Keys Daffer & Kordzik PLLC
7004 Bee Cave Rd.
Bldg. 1, Suite 110
Austin, TX 78746
NAN JIANG
03/16/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
kkordzik@ mathesonkeys.com
claney @ mathesonkeys .com
kdaffer @ mathesonkeys. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte NAN JIANG and ZVI YANIV
Appeal 2016-001454
Application 13/570,6121
Technology Center 1700
Before RAE LYNN P. GUEST, GEORGE C. BEST, and
DONNA M. PRAISS, Administrative Patent Judges.
PRAISS, Administrative Patent Judge.
DECISION ON APPEAL2
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134 from the Examiner’s
decision to reject claims 11—28 under 35 U.S.C. § 103(a) as follows:
1 The real party in interest is identified by Appellants as Applied Nanotech
Holdings, Inc. App. Br. 1.
2 In this decision, we refer to the Specification filed Aug. 9, 2012 (“Spec.”),
the Final Office Action appealed from mailed Oct. 9, 2014 (“Final Act.”),
the Appeal Brief filed Apr. 9, 2015 (“App. Br.”), the Examiner’s Answer
mailed Sept. 18, 2015 (“Ans.”), and the Reply Brief filed Nov. 16, 2015
(“Reply App. Br.”).
Appeal 2016-001454
Application 13/570,612
1. Claims 11—13, 15, 16, and 21—26 over Reis3 and Mazzochette4;
2. Claim 14 over Reis, Mazzochette, and Trujillo5; and
3. Claims 17—20, 27, and 28 over Reis, Mazzochette, and Li6.
We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
The subject matter on appeal relates to “[tjhermal management
materials with high thermal conductivity, high thermal diffusivity,
machineability, and/or low coefficient of thermal expansion.” Spec. 1:5—6.
More particularly, a method of anodizing an aluminum layer deposited on a
graphite substrate results in an aluminum oxide layer and “creates a non-
conductive dielectric layer which makes the material easier to integrate with
electronic components (including conductive circuitry) that need a non-
conductive surface.” Id. 3:7—14. Claim 11 is illustrative (disputed
limitations italicized):
11. A method comprising:
depositing a dielectric layer on a graphitic substrate; and
depositing electrical circuitry on the dielectric layer in a manner
so that all thermal pathways between all of the electrical
circuitry deposited on the dielectric layer and the graphitic
substrate include the dielectric layer as part of the thermal
pathways.
Claims App’x at App. Br. 10.
3 Reis et al., US 7,505,275 B2, iss. Mar. 17, 2009 (“Reis”).
4 Mazzochette et al., US 2005/0161682 Al, pub. July 28, 2005
(“Mazzochette”).
5 Trujillo et al., US 2012/0097961 Al, pub. Apr. 26, 2012 (“Trujillo”).
6 Li et al., US 2009/0311440 Al, pub. Dec. 17, 2009 (“Li”).
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Application 13/570,612
Independent claims 19 and 21 are similar to claim 11, but do not include the
italicized limitation. Instead, claim 19 further recites “depositing a
conductive ink on the dielectric layer, and then photo sintering the
conductive ink to form conductive circuitry” and claim 21 recites “thermal
pathways between the electrical circuitry deposited on the dielectric layer
and the graphitic substrate pass through the dielectric layer.” Id. at 11.
Appellants do not separately argue the patentability of the claims for
each rejection. App. Br. 4—9. In accordance with 37 C.F.R.
§ 41.37(c)(l)(iv), claims 12, 13, 15, and 21, 22, 25, and 26 will stand or fall
together with independent claim 11 and claims 18, 27, and 28 will stand or
fall together with claim 17.
OPINION
Rejection 1: Reis and Mazzochette
Regarding claims 11—13, 15, 16, and 21—26, the Examiner finds that
Reis discloses all of the claimed limitations except that Reis “fails to teach
the thermal pathway being the dielectric material and not a conductive via.”
Ans. 2. The Examiner further finds that Mazzochette teaches “a low thermal
resistance insulation layer can electrically insulate other areas of die from
the base while permitting heat passage (abstract).” Id. at 3 (citing
Mazzochette Figs. 1 and 4, showing a dielectric layer 12 between the
electrical circuitry 10 and a metal base 11 with a thermal connector pad 16,
and Fig. 6, showing a ceramic layer 17 with vias as part of the passageway
for heat dissipation). The Examiner finds “it would have been obvious for
one skilled in the art at the time the invention was made to have modified
[Reis’s] heat sink to include pathways through the dielectric layer as
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Application 13/570,612
evidenced by [Mazzochette] with the expectation of achieving similar
success of heat dissipation thereof.” Id. The Examiner also finds that
Mazzochette discloses ceramic layer 17 as required by claim 16, which
recites “wherein the depositing of the dielectric layer on the graphitic
substrate further comprises coating a ceramic material as the dielectric layer
on the graphitic substrate.” Id.
Appellants contend that the Examiner’s rejection of claim 11 is in
error because “Claim 11 recites that ah of the pathways by which thermal
heat is transferred form the electrical circuitry to the graphitic substrate must
pass through the dielectric layer.'” App. Br. 4 (emphasis added). Thus,
although the language of claim 11 does not define “thermal pathways” that
“pass through” the dielectric layer, Appellants are interpreting claim 11
similar to the language of claims 20 and 21 which expressly recite that the
thermal pathways “pass through the dielectric layer.” According to
Appellants, “Reis would motivate one of ordinary skill in the art to require
the utilization of a via.” Id. at 5. Appellants also argue that “the claims
prohibit such a use of a thermal slug or via.” Id. at 6.
Regarding claim 16, Appellants contend that “[t]he ceramic layer 17
in Mazzochette does not function as the dielectric layer.” Id. (citing
Mazzochette 130). Regarding claims 23 and 24, Appellants contend that
“[t]he Examiner has not in any way addressed this specific claim language in
the Office Action.” Id.
The Examiner responds that “the claims as written do not preclude
‘some’ of the heat dissipation going thru the dielectric layer and the thermal
via which is taught by the combination of references especially since the
dielectric layer in the reference and the claims includes anodized
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Application 13/570,612
aluminum.” Ans. 5. Stated another way, the Examiner finds that “the
claims are not limited to the definition of thru being only a dielectric layer
and not a dielectric layer including a thermal via.” Id. The Examiner also
finds that independent claims 19 and 21 do not recite properties for “all”
thermal pathways. Id.
In the Reply Brief, Appellants do not dispute that claims 19 and 21 do
not recite properties for “all” thermal pathways, but argue that claim 20
which depends from claim 19 requires that “the sole thermal pathway
between all of the conductive circuitry deposited on the dielectric layer and
the graphitic substrate is through the dielectric layer.” Reply Br. 2.
Appellants further contend that the Examiner’s claim construction “is
unreasonably broad” because “Claims 11—18 do preclude any heat
dissipation through any thermal vias since all thermal pathways going
through the dielectric layer means that no thermal pathways remain for
passing through the thermal vias.” Id. at 1—2. Appellants also restate that
the claim limitations recited in claims 23 and 24 are not specifically
addressed by the Examiner. Id. at 2.
The Appellants’ arguments fail to identity a reversible error in the
Examiner’s rejection. See In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011)
(requiring appellant to identify reversible error).
We start with the Appellants’ argument concerning the proper claim
interpretation for “all thermal pathways . . . include the dielectric layer as
part of the thermal pathways” in claim 11 and “thermal pathways . . . pass
through the dielectric layer” in claim 21 because, in our view, it raises an
issue that is dispositive of this rejection. “[Djuring patent prosecution when
claims can be amended, ambiguities should be recognized, scope and
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breadth of language explored, and clarification imposed.” In re Zletz, 893
F.2d 319, 321 (Fed. Cir. 1989). “Only in this way can uncertainties of claim
scope be removed, as much as possible, during the administrative process.”
Id. at 322. “[A]s applicants may amend claims to narrow their scope, a
broad construction during prosecution creates no unfairness to the applicant
or patentee.” In re ICON Health & Fitness, Inc., 496 F.3d 1374, 1379 (Fed.
Cir. 2007).
Appellants’ arguments are unpersuasive because the Examiner’s
finding that the disputed claim limitations “do not preclude . . . heat
dissipation going through the dielectric layer and the thermal via” (Ans. 5) is
reasonable and not inconsistent with the Specification. Regarding support in
the Specification for the disputed language of claim 11, Appellants assert
that “Figure 5 shows examples of all thermal pathways passing through the
dielectric graphitic substrates obtained by photo sintering of copper nano­
inks” (App. Br. 2) and cite the portion of the Specification that describes
Figure 5 (Spec. 5:20—25) in the Amendment to Appeal Brief filed June 18,
2015 (“Amendment” at 2). The cited portion of the Specification, as well as
the portion of the Specification describing the Figures, describe Figures 5A
and 5B as digital photographs of conductive circuitry formed on the
dielectric/graphite substrates. Spec. 2:10—12, 5:20—25. Thus, the focus of
Figure 5 is the circuitry atop the dielectric layer, not the cross-section of the
dielectric layer. Even if Figure 5 were to show that the dielectric layer does
not include thermal vias, it would not be limiting because it is merely an
exemplary embodiment. Our reviewing court “has repeatedly cautioned
against limiting the claimed invention to preferred embodiments or specific
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Application 13/570,612
examples in the specification.” Williamson v. Citrix Online, LLC, 792 F.3d
1339, 1346-47 (Fed. Cir. 2015).
Furthermore, page 4 of the Specification indicates that the thermal
dissipation path is through the “non-oxidized regions,” and not through the
anodized dielectric regions while “[t]he oxidized area(s) provide the
electrical insulation as needed by electrical component(s).” Spec. 4:3—6
(“the non-oxidized regions provid[e] conduction and thermal dissipation
paths.”). Therefore the Examiner’s claim construction of “dielectric layer”
as not excluding a thermal via is not inconsistent with the Specification.
Furthermore, Appellants have not directed us to any evidence in the
Specification and the claims that would limit the dielectric layer to only the
anodized portion of the dielectric layer.
Appellants do not dispute the Examiner’s finding that claims 19 and
21 do not include the limitation “all thermal pathways.” Nor do Appellants
dispute the Examiner’s findings that Reis discloses “a graphite/dielectric
material laminate” where the dielectric layer “can include a polymer or
metal layer such as aluminum which has been anodized” (Ans. 2).
Appellants do not adequately explain how the Examiner’s findings regarding
the physical structure of the graphite and dielectric material being a laminate
fail to address the limitations of claim 23 and 24 which relate to the position
of the dielectric layer relative to the graphitic substrate.
Regarding the step recited in claim 16 of “coating a ceramic material
as the dielectric layer on the graphitic substrate,” Appellants do not dispute
the Examiner’s finding that Mazzochette “teaches ceramic layers” (Ans. at
3). Appellants also do not dispute the Examiner’s finding that
Mazzochette’s Figures 1 and 4, showing a dielectric layer 12 between the
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electrical circuitry 10 and a metal base 11 with a thermal connector pad 16,
and Fig. 6, showing a ceramic layer 17 with vias as part of the passageway
of heat dissipation, teach “a low thermal resistance insulation layer can
electrically insulate other areas of die from the base while permitting heat
passage (abstract).” Ans. at 3. Appellants only dispute whether
Mazzochette’s ceramic layer on the graphitic substrate “fimction[s] as the
dielectric layer” in view of Mazzochette’s teaching that “the ceramic layer
can include circuit components for powering, controlling, protecting and
interconnecting LEDs.” App. Br. 6 (citing Mazzochette 130). Appellants’
argument is not persuasive because (1) it does not rebut the Examiner’s
finding that Mazzochette layers the ceramic material onto the graphitic
substrate, (2) it does not rebut the Examiner’s finding that the embodiments
of Figures 1 and 2, on the one hand, and Figure 6, on the other hand, teach
low thermal resistance insulating layers that can electrically insulate while
also permitting heat passage, and (3) it does not adequately explain why a
skilled artisan would not understand the ceramic layer including thermal vias
of Mazzochette’s Figure 6 to also function as a “dielectric layer” as recited
in claim 16 and shown in Figures 1 and 4 without thermal vias. Therefore,
even if Mazzochette’s ceramic layer “can include circuit components for
powering, controlling, protecting and interconnecting LEDs” as asserted by
Appellants, its layering on the graphitic substrate, as found by the Examiner
and required by claim 16, is supported by the preponderance of the evidence
in this record.
In the absence of any error in the Examiner’s findings, we do not find
the Appellants’ arguments sufficient to justify a reversal of the Examiner’s
rejection. In re Jung, 637 F.3d 1356 at 1365.
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In sum, Appellants have not persuaded us of reversible error in the
Examiner’s finding that claims 11—13, 15, 16, and 21—26 would have been
obvious in view of the combination of Reis and Mazzochette.
Rejection 2: Reis, Mazzochette, and Trujillo
Claim 14 depends from claim 11. The Examiner finds that Reis as
modified by Mazzochette “fail[s] to teach using a mask to cover the metal
layer prior to anodizing the aluminum layer” as required by claim 14. Ans.
3. The Examiner further finds that “it would have been obvious for one
skilled in the art at the time the invention was made to have modified [Reis]
in combination with [Mazzochette’s] process to incorporate a mask for
forming patterned dielectric layer as evidence by [Trujillo] with the
expectation of achieving selective anodization if desired.” Id. at 3^4 (citing
Trujillo, Abstr., Fig. 1).
Appellants’ argument concerning the Examiner’s rejection of claim 14
is that the “claim is patentable since it depends upon an allowable claim.”
App. Br. 7.
We are not persuaded by Appellants’ argument that claim 14 is
patentable because claim 11 is patentable for the same reasons discussed
above in connection with claim 11.
In sum, Appellants have not persuaded us of a reversible error in the
Examiner’s finding that claim 14 would have been obvious in view of Reis
in combination with Mazzochette and Trujillo.
Rejection 3: Reis, Mazzochette, and Li
Regarding claims 17—20, 27, and 28, the Examiner finds that Reis as
modified by Mazzochette “fail[s] to teach applying conductive ink and
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curing the ink to [form] the conductive layer.” Ans. 4. The Examiner
further finds that “it would have been obvious for one skilled in the art at the
time the invention was made to have modified [Reis] in combination with
[Mazzochette’s] process to incorporate a conductive ink coating and
photo/thermal curing step as evidence by [Li] with the expectation of
achieving a conductive layer thereon.” Id. (citing Li, Abstr., || 107, 130).
Appellants contend that the Examiner erred in rejecting claims 17 and
19 because
the Examiner has provided no reasoning as to why one of
ordinary skill in the art would desire to incorporate a
photosintering process disclosed in Li into the invention
disclosed in Reis. Nowhere within Reis is there any teaching or
suggestion that any of the circuitry, such as circuitry 400, may be
deposited as a conductive ink that is thereafter sintered,
especially photosintered.
App. Br. 7. Appellants further assert that the Examiner has made
inconsistent findings regarding whether “Reis teaches applying a conductive
ink . . . but does not teach post-heating.” Id. at 8. Appellants also argue that
claim 20 is patentable for the reasons discussed above in connection with
claim 11.
We are not persuaded by Appellants’ arguments because Appellants
do not dispute that Reis teaches applying a conductive ink. Moreover, the
Examiner’s finding (Ans. 2) that Reis discloses “[t]he conductive layer (400)
can be applied with the use of a conductive ink (col. 4, lines 42^48)” is
supported by the record. That the Examiner further finds that the
combination of Reis and Mazzochette fails to teach both applying then
photosintering the conductive ink to form conductive circuitry as required by
claim 17 is not inconsistent with the Examiner’s findings as to Reis nor
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Application 13/570,612
contradicted by the record. In view of Reis’s teaching that the conductive
circuitry can be formed using conductive ink, we are not persuaded that the
Examiner’s combination with Li is imbued with impermissible hindsight
because Li evidences that one of ordinary skill in the art would have known
that the photocuring step makes such inks conductive..
We also are not persuaded by Appellants’ argument that the Examiner
erred in rejecting claim 20 over the combination of Reis, Mazzochette, and
Li for the reasons discussed above in connection with claim 11. Because the
claimed “all thermal pathways” of claim 11 are not limited to pathways
through an anodized portion of the dielectric layer, we similarly find that
“the sole thermal pathway ... is through the dielectric layer” recited in claim
20 is also interpreted to include all pathways through the dielectric layer and
thus is not limited only to pathways through an anodized portion of the
dielectric layer for the same reasons discussed above with respect to the
dielectric layer of claim 11. Based on this record, we also are not persuaded
by Appellants that a thermal pathway, let alone the claimed “sole thermal
pathway”, cannot also be electrically conductive. See Spec. 4:3—6 (“the non-
oxidized regions provid[e] conduction and thermal dissipation paths.”).
Moreover, Appellants have not shown the Specification to limit the term
“pathway” more narrowly than the entire region between the electrical
circuitry and the graphitic substrate. In this regard, Mazzochette’s figure 6
shows both the dielectric/insulating/ceramic material (17) and the thermal
vias as being directly below the electrical component/LED (10).
In sum, Appellants have not persuaded us of a reversible error in the
Examiner’s finding that claims 17—20, 27, and 28 would have been obvious
in view of Reis, Mazzochette, and Li.
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Application 13/570,612
CONCLUSION
We sustain the Examiner’s rejections.
DECISION
The Examiner’s decision is affirmed.
TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1).
AFFIRMED
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