Ex Parte Jia et al

Patent Trials and Appeals Board

Feb 29, 2016

12635550 - (D) (P.T.A.B. Feb. 29, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/635,550 12/10/2009
121312 7590 03/03/2016
Foley & Lardner LLP/ Broadcom Corporation
3000 K Street N.W
Suite 600
Washington, DC 20007-5109
FIRST NAMED INVENTOR
Yunwei Jia
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
106861-0312 9550
EXAMINER
TRAN, TRANGU
ART UNIT PAPER NUMBER
2422
NOTIFICATION DATE DELIVERY MODE
03/03/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
ipdocketing@foley.com
cmckenna@foley.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte YUNWEI JIA and PAUL WIERCIENSKI
Appeal2014-003105
Application 12/635,550
Technology Center 2400
Before ST. JOHN COURTENAY III, JAMES R. HUGHES and
CATHERINE SHIANG, Administrative Patent Judges.
COURTENAY, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner's Final
Rejection of claims 1-20, which are all the claims pending in the
application. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
Invention
The claimed invention on appeal is directed to "parallel processing for
providing high resolution frames from low resolution frames." (Spec. i-f 4).
Appeal2014-003105
Application 12/635,550
Illustrative Claim
1. A system for receiving lower resolution frames and generating
higher resolution frames, said system comprising:
[L 1] an ups amp ling circuit that generates an ups amp led frame
from a particular lower resolution frame;
a first circuit that maps blocks from lower resolution frames
that are proximate to the particular lower resolution frame to the
particular lower resolution frame; and
[L2] a second circuit that updates the ups amp led frame with
two or more blocks from at least one of the lower resolution
frames that are proximate to the particular lower resolution
frame.
(Emphasis added regarding the contested limitations, labeled as "L 1" and
"L2").
Rejection
Claims 1-20 are rejected under 35 U.S.C. § 102(b) as anticipated by
Beric et al (US 2008/0204602 Al; published August 28; 2008).
Contentions
Regarding the anticipation rejection of claim 1, Appellants contest the
Examiner's rejection of limitation L2. (App. Br. 9). Appellants particularly
contend, inter alia:
Eerie is entirely silent, however, with regard to the motion estimator
106 comprising a circuit that updates an up sampled frame.
Specifically, Eerie does not describe that the motion estimator 106
updates an upsampled frame generated by the "picture-rate up-
conversion applications," as suggested in the Office Action and
Advisory Action. In contrast, Eerie merely describes at paragraph
[0003] that video-processing devices employing motion estimation are
used in picture-rate up-conversion applications, without describing
that the motion estimator 106 (or any other element) updates an
upsampled frame "with two or more blocks from at least one of the
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Application 12/635,550
lower resolution frames that are proximate to the particular lower
resolution frame," as defined by claim 1.
The Examiner disagrees (Ans. 6-7):
As discussed in the previous office actions, Beric discloses in
paragraph #0003 that the motion estimation is used in picture-rate up-
conversion applications, in page 5, paragraph #0096 that "During
operation, two consecutive images stored in memory sections 102.1
and 102.2 of main memory 102 are used to determine motion
vectors for each pixel block of a currently processed image. For
illustration purposes, it is assumed that the memory section 102.2
contains a currently processed image and memory section 102.1
contains an image immediately preceding that stored in section
102.2 in an image sequence", and in paragraph #0100 that" video
[sic] processing device 100 is a motion estimation device, however,
motion estimation is used in various video processing tasks such as
motion compensated filtering for noise reduction, motion
compensated prediction for coding, and motion compensated
interpolation for video format conversion ... ". From these passages,
it is clear that the motion estimation is used in picture-rate up-
conversion applications via interpolation and that the motion
estimation is used both pixel blocks of the currently processed image
and image immediately preceding the currently processed image.
Since the motion estimation is used [in] both pixel blocks of the
currently processed image and [the] image immediately preceding the
currently processed image, the motion estimation of Beric et al[.]
would update the picture-rate up-conversion applications. Thus, the
motion estimation of Beric et al[.] is anticipated the claimed "a
second circuit that updates an upsampled frame with two or more
blocks from at least one lower resolution frame".
ISSUE
Issue: Under § 102, did the Examiner err by finding Beric expressly
or inherently discloses the contested limitations:
[L 1] an ups amp ling circuit that generates an ups amp led frame from a
particular lower resolution frame; and
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Application 12/635,550
[L2] a second circuit that updates the upsampledframe with two or
more blocks from at least one of the lower resolution frames
that are proximate to the particular lower resolution frame[,]
within the meaning of claim 1? (Emphasis added).
ANALYSIS
We focus our analysis on contested limitation L2, and need not reach
contested limitation L 1 to decide this appeal.
The Examiner responds to Appellants' contentions regarding
limitation L2, and refers generally to paragraphs [0003], [0096], and [0100]
of Beric. The Examiner finds: "[s]ince the motion estimation is used [in]
both pixel blocks of the currently processed image and [the] image
immediately preceding the currently processed image, the motion estimation
of Beric et al[.] would update the picture-rate up-conversion applications."
(Ans. 7). We note paragraph 3 of Beric discloses:
[0003] Video-processing devices employing ME [Motion Estimation]
are used in television devices, for instance for De-interlacing and
picture-rate up-conversion applications. ME is also used for video
data encoding.
However, the Examiner provides no direct mapping to an express
description in Beric regarding the contested L2 limitation:
a second circuit that updates the upsampled frame with two or
more blocks from at least one of the lower resolution frames
that are proximate to the particular lower resolution frame ....
(Claim 1 ).
Beric' s paragraph 96 (Fig. 1) discloses "two consecutive images
stored in memory sections 102 .1 and 102 .2 of main memory 102 [that] are
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Application 12/635,550
used to determine motion vectors for each pixel block of a currently
processed image." However, we find paragraph 96 does not describe a
circuit with the contested L2 limitation. We also find the description in
Beric (at i-f l 00) does not provide the missing contested claimed features.
Nor does the Examiner provide any supporting factual evidence or
technical reasoning explaining how limitation L2 is inherently disclosed by
Beric. '"In relying upon the theory of inherencyi the examiner must provide
a basis in fact and/or tec1rnica1 reasoning to reasonably support the
determination that the aHeged!y inherent characteristic necessarify nows
from the teachings of the applied prior art~~ Ex parte Levy, 17 USPQ2d
1461, 1464 (BPAI 1990) (emphasis added).
Although motion estimation may be used as input to picture-rate up-
conversion applications, as suggested by Examiner (Ans. 7, Beric i-f3), there
is no evidence provided that contested limitation L2 necessarily flows from
the relied-upon features of Beric's disclosure. 1
We additionally find the Examiner's statement of rejection (Ans. 2-3)
does not clearly map each element of claim 1 (including at least contested
limitations LI and L2) to the corresponding specific features found in Beric.
We reproduce the Examiner's rejection of claim 1 in its entirety:
In considering claim 1, Beric et al [.] discloses all the claimed subject
matter, note 1) the claimed an upsampling circuit that generates an
upsampled frame from a particular lower resolution frame is met by
the video processing device 100 (Fig. 1, page 1, paragraph #0010 to
1 "Inherency ... may not be established by probabilities or possibilities. The
mere fact that a certain thing may result from a given set of circumstances is
not sufficient." In re Robertson, 169 F.3d 743, 745, (Fed. Cir. 1999)
(internal citations omitted).
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Application 12/635,550
page 2, paragraph #0026), 2) the claimed a first circuit that maps
blocks from lower resolution frames that are proximate to the
particular lower resolution frame to the particular lower resolution
frame is met by the motion estimator (Figs. 1-2, page 2, paragraph
#0029 to paragraph #0034 and page 5, paragraph #0092 to page 7,
paragraph #0109), and 3) the claimed a second circuit that updates the
upsampled frame with two or more blocks from at least one of the
lower resolution frames that are proximate to the particular lower
resolution frame is met by updating the motion vector candidate (Figs.
1-2, page 6, paragraph #0101 to page 7, paragraph #0118).
Final Act. 4.
In reviewing the statement of rejection (id.), Appellants' arguments in
the Brief (7-9), and the Examiner's responsive arguments (Ans. 5-7), we
find the Examiner paints with a broad brush in making the anticipation
rejection. In addressing contested limitation L2, the Examiner refers to
"(Figs. 1-2, page 6, paragraph #0101 to page 7, paragraph #0118)" ofBeric.
(Final Act. 4). Without further specificity, it is unclear what the Examiner is
relying on for an express or inherent description of the contested limitations.
We decline to make speculative assumptions regarding the Examiner's
intended mapping regarding at least contested limitation L2 of claim 1.
We note that the Board is a reviewing body and not a place of initial
examination. The PTO bears the initial burden of showing a prima facie
case. In re Sullivan, 498 F.3d 1345, 1351 (Fed. Cir. 2007). The rigorous
requirements of anticipation require a clear mapping of each claim limitation
to the corresponding feature found in the reference, which the Examiner
must identify with particularity.
Only when a prima facie case is established by the Examiner, does the
burden then shift to the Applicants to come forward with evidence and/or
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argument supporting patentability. In re Glaug, 283 F.3d 1335, 1338 (Fed.
Cir. 2002). The prima facie burden has not been met and the rejection does
not adhere to the minimal requirements of 35 U.S.C. § 132 "when a rejection
is so uninformative that it prevents the applicant from recognizing and
seeking to counter the grounds for rejection." Chester v. Miller, 906 F.2d
1574, 1578 (Fed. Cir. 1990).
This reasoning is applicable here. For essentially the same reasons
articulated by Appellants (App. Br. 9), as discussed above, we agree the
Examiner has failed to set forth a prima facie case of anticipation. Because
the Examiner has not construed and mapped at least contested limitation L2
to the corresponding features in Beric with particularity, we find the
Examiner has not shown by a preponderance of the evidence that Beric
anticipates at least contested limitation L2, as recited in claim 1.
Remaining independent claims 9 and 1 7 each recite contested
limitation L2 in commensurate form. Therefore, for the aforementioned
reasons, we reverse the Examiner's anticipation rejection of independent
claims 1, 9, and 17 over Beric. Because we have reversed the rejection of
each independent claim on appeal, we also reverse the anticipation rejection
of each associated dependent claim.
Conclusion
On this record, and by a preponderance of the evidence, we are
persuaded the Examiner erred in rejecting claims 1-20 under§ 102(b), for at
least the reasons argued on page 9 of the Brief, as further discussed above.
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DECISION
We reverse the Examiner's rejection of claims 1-20 under§ 102(b).
REVERSED
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