10651801 (B.P.A.I. Aug. 31, 2010)

Ex Parte Jeddeloh

Board of Patent Appeals and InterferencesAug 31, 2010

10651801 (B.P.A.I. Aug. 31, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 10/651,801 08/28/2003 Joseph M. Jeddeloh 501322.01 9730 27076 7590 08/31/2010 DORSEY & WHITNEY LLP INTELLECTUAL PROPERTY DEPARTMENT Columbia Center 701 Fifth Avenue, Suite 6100 SEATTLE, WA 98104-7043 EXAMINER NGUYEN, TANH Q ART UNIT PAPER NUMBER 2182 MAIL DATE DELIVERY MODE 08/31/2010 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ Ex parte JOSEPH M. JEDDELOH ____________ Appeal 2009-005199 Application 10/651,801 Technology Center 2100 ____________ Before HOWARD B. BLANKENSHIP, JEAN R. HOMERE, and ST. JOHN COURTENAY III, Administrative Patent Judges. BLANKENSHIP, Administrative Patent Judge. DECISION ON APPEAL1 1 The two-month time period for filing an appeal or commencing a civil action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing, as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE” (paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery mode) shown on the PTOL-90A cover letter attached to this decision. Appeal 2009-005199 Application 10/651,801 2 STATEMENT OF THE CASE This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final rejection of claims 1, 2, 4-10, 12, 14-24, and 26, which are all the claims remaining in the application. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. Invention Appellant’s invention relates to a memory hub architecture that routes memory requests and responses between a system controller and memory devices via a memory hub. Spec. ¶ [006]. The memory hub includes a direct memory access (DMA) engine. Id. ¶ [030]. Representative Claim 1. An integrated circuit memory hub for use with a memory device, the memory hub comprising: a link interface for receiving memory requests, the link interface being fabricated on a semiconductor substrate; a memory device interface fabricated on the semiconductor substrate and coupled to the link interface, the memory device interface outputting write memory requests and write data responsive to signals received from the link interface, the memory device interface further outputting read memory requests responsive to signals received from the link interface and transmitting signals to the link interface responsive to read data received in response to the read memory requests; a data mining module fabricated on a semiconductor substrate and coupled to the link interface and to the memory device interface, the data mining module including a direct Appeal 2009-005199 Application 10/651,801 3 memory access engine coupled to the link interface, the direct memory access engine being operable to receive search information identifying a memory area to be searched, the data mining module being operable to receive through the link interface information about a data search including at least one item of search data, the direct memory access engine being operable to repetitively generate and couple to the memory device interface read memory requests for accessing a range of memory locations identified by the search information to cause the memory device interface to repetitively output read memory requests without requiring that corresponding read memory requests be provided to the data mining module, the data mining module further being operable to receive read data from the memory device interface responsive to each of the read memory requests; and a comparator coupled to receive a respective item of the received search data and being coupled to receive the read data, the comparator being operable to compare the read data to the respective item of the received search data and provide a hit indication in the event of a match. Prior Art Thoulon US 5,621,883 Apr. 15, 1997 Dennin US 6,401,149 Jun. 4, 2002 O’Reilly WO 98/57489 Dec. 17, 1998 Appellant’s admitted prior art at paragraph [030] of the Specification (“AAPA”). Examiner’s Rejection Claims 1, 2, 4-10, 12, 14-24, and 26 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over O’Reilly, AAPA, Dennin, and Thoulon. Appeal 2009-005199 Application 10/651,801 4 Claim Groupings Based on Appellant’s arguments in the Appeal Brief, we will decide the appeal on the basis of claim 1. See 37 C.F.R. § 41.37(c)(1)(vii). FINDINGS OF FACT We refer to, and rely on, the Examiner’s findings set out in the Final Rejection and the Answer. PRINCIPLES OF LAW “[W]hen a patent ‘simply arranges old elements with each performing the same function it had been known to perform’ and yields no more than one would expect from such an arrangement, the combination is obvious.” KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 417 (2007) (quoting Sakraida v. Ag Pro, Inc., 425 U.S. 273, 282 (1976)). The operative question is “whether the improvement is more than the predictable use of prior art elements according to their established functions.” Id. ANALYSIS The Examiner finds that O’Reilly teaches all the limitations of instant claim 1 except for the data mining module “including a direct memory access engine” coupled to the link interface. The Examiner submits that O’Reilly, in view of the teachings of any of AAPA, Dennin, or Thoulon, demonstrates that it would have been obvious to couple a DMA engine to the link interface as claimed. Appeal 2009-005199 Application 10/651,801 5 Appellant contends, however, that none of the applied prior art discloses or suggests using a DMA engine in an integrated circuit memory hub. In particular, Appellant admits that all of the cited prior art uses a DMA engine for directly accessing a memory device. App. Br. 18. Appellant alleges (improper) hindsight in the rejection because none “disclose a DMA engine in a memory hub.” Id. However, “suggestion” to incorporate a DMA engine in a memory hub need not be expressly stated in some prior art reference. The “suggestion” for integrating a DMA engine in a memory hub follows from the art-recognized efficiencies in integrating system components. [A]n implicit motivation to combine exists not only when a suggestion may be gleaned from the prior art as a whole, but when the “improvement” is technology-independent and the combination of references results in a product or process that is more desirable, for example because it is stronger, cheaper, cleaner, faster, lighter, smaller, more durable, or more efficient. Because the desire to enhance commercial opportunities by improving a product or process is universal -- and even common-sensical -- we have held that there exists in these situations a motivation to combine prior art references even absent any hint of suggestion in the references themselves. In such situations, the proper question is whether the ordinary artisan possesses knowledge and skills rendering him capable of combining the prior art references. Dystar Textilfarben GmbH v. C.H. Patrick Co., 464 F.3d 1356, 1368 (Fed. Cir. 2006). As the Examiner finds, it was well known in the art to integrate electronic components in a single integrated circuit fabricated on a semiconductor substrate in order to reduce the size and the cost of the Appeal 2009-005199 Application 10/651,801 6 devices. However, Appellant has provided no evidence tending to show that placing a DMA engine in a memory hub was “uniquely challenging or difficult for one of ordinary skill in the art.” Leapfrog Enters., Inc. v. Fisher- Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007) (citing KSR, 550 U.S. at 419). To the contrary, the evidence shows that the ordinary artisan knew how to integrate a DMA controller with a synchronous DRAM (memory) controller. Dennin Fig. 1; col. 4, l. 66 - col. 5, l. 1. The evidence thus suggests there was nothing “uniquely challenging or difficult for one of ordinary skill in the art” to incorporate a DMA engine in a memory hub. Appellant also alleges, particularly in the Reply Brief, advantages in placing a DMA engine in a memory hub as opposed to somewhere else. However, Appellant does not allege, let alone show, that the purported advantages would have been surprising or unexpected to one of ordinary skill in the art, rather than the predictable use of prior art elements according to their established functions. We are therefore not persuaded that claim 1 has been rejected in error. We sustain the § 103(a) rejection of claim 1. Claims 2, 4-10, 12, 14-24, and 26 fall with claim 1. DECISION The rejection of claims 1, 2, 4-10, 12, 14-24, and 26 under 35 U.S.C. § 103(a) as being unpatentable over O’Reilly, AAPA, Dennin, and Thoulon is affirmed. Appeal 2009-005199 Application 10/651,801 7 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 41.50(f). AFFIRMED msc DORSEY & WHITNEY LLP INTELLECTUAL PROPERTY DEPARTMENT Columbia Center 701 Fifth Avenue, Suite 6100 SEATTLE WA 98104-7043