Ex Parte Jang

Board of Patent Appeals and Interferences

Jul 30, 2012

11191376 (B.P.A.I. Jul. 30, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
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Ex parte SEONG-JIN JANG
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Appeal 2010-002530
Application 11/191,376
Technology Center 2800
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Before ROBERT E. NAPPI, KALYAN K. DESHPANDE, and
JASON V. MORGAN, Administrative Patent Judges.

MORGAN, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2010-002530
Application 11/191,376

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STATEMENT OF THE CASE
Introduction
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1, 4, 5, and 19 – 22. Claims 2, 3, 8, and 12 – 18 are
canceled. See App. Br. 3. Claims 6, 7, and 9 – 11 are allowed. See Ans. 2.
We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
Invention
The invention is directed to a circuit for generating a reference voltage
that includes a first reference voltage generating circuit disposed outside a
chip and a second reference voltage generating circuit disposed inside the
chip. See Abstract.
Exemplary Claim
1. A circuit for generating a reference voltage for use in a
semiconductor device, the circuit comprising:
an external reference voltage generating circuit, disposed
outside a chip, configured to output a first reference voltage,
based on an external power supply voltage, to an output
terminal of the external reference voltage generating circuit;
and
an internal reference voltage generating circuit, disposed
inside the chip, configured to output a second reference voltage,
based on an internal power supply voltage of the chip, to an
output terminal of the internal reference voltage generating
circuit, wherein the internal reference voltage generating circuit
includes:
at least one pull-up resistor coupled between a first
node and the output terminal of the internal reference
voltage generating circuit, wherein the first node is
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Application 11/191,376

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electrically coupled to the internal power supply voltage
of the chip; and
at least one pull-down resistor coupled between a
second node and the output terminal of the internal
reference voltage generating circuit, wherein a voltage at
the second node is lower than a voltage at the first node,
and wherein the reference voltage corresponding to an
average value between a voltage level corresponding to a
logic high and a voltage level corresponding to a logic
low is present at a node where the output terminal of the
external reference voltage generating circuit is coupled to
the output terminal of the internal reference voltage
generating circuit.
Rejection
The Examiner rejects claim 1 under 35 U.S.C. § 103(a) as being
unpatentable over Gerber (US 5,998,983; Dec. 7, 1999). See Ans. 3.
The Examiner rejects claims 4, 5, and 19 – 22 under 35 U.S.C.
§ 103(a) as being unpatentable over Gerber and Tauber (US 2004/0119524
A1; June 24, 2004). See Ans. 4; see also Fin. Rej. 4 – 8.
ISSUE
Whether the Examiner has shown that it would have been obvious to
an artisan of ordinary skill to modify Gerber by separating Gerber’s circuit
into two separate circuits.
ANALYSIS
In rejecting independent claim 1, the Examiner relies on Gerber to
teach or suggest a circuit for generating a reference voltage for use in a
semiconductor device. See Ans. 3. The Examiner acknowledges that Gerber
“does not show that the first reference voltage generating circuit . . . is
outside the chip . . . . [But finds that] it is well known in the art that a circuit
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Application 11/191,376

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can be separated into two different circuits supplied by separate power
supplies for reducing the generated heat.” Id. Appellant disputes the
Examiner’s finding that it would have been obvious to separate Gerber’s
circuit, citing to teachings in Gerber showing that an object of Gerber is to
allow for better integration (i.e., to use fewer circuits) and contending that
the Examiner’s rejection relies on hindsight reasoning. See App. Br. 8 – 10;
see also Reply Br. 11.
The Examiner responds to Appellant’s contentions by referring to
Imamura (US 2008/0315401 A1; Dec. 25, 2008) Figure 2 to clarify the
Examiner’s finding that “it is obvious to one of ordinary skill in the art that a
circuit can be separated into two different circuits for reducing the head
dissipation.” Ans. 4. However, Imamura was not previous relied upon in
rejecting the claimed invention. Moreover, Imamura’s filing date (June 18,
2008) is nearly three years after the filing date for Appellant’s application
(July 28, 2005). Because Imamura was not made of record during
examination of the application and is not prior art, we will not consider it as
evidence in support of the Examiner’s rejection.
Since the Examiner provides no other explanation or evidence that
persuasively shows that it would have been obvious to modify Gerber’s
circuit by separating it into two circuits, we will not sustain the Examiner’s
35 U.S.C. § 103(a) rejection of claim 1. The Examiner’s 35 U.S.C. § 103(a)
rejection of claims 4, 5, and 19 – 22 relies on similar modifications to
Gerber and the Examiner does not show that Tauber cures the deficiencies of
Gerber. See Ans. 4 and Fin. Rej. 7 – 8. Therefore, we also will not sustain
the Examiner’s 35 U.S.C. § 103(a) rejection of claims 4, 5, and 19 – 22.
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Application 11/191,376

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The Examiner also objects to claim 1 for failing to provide proper
antecedent basis. See Fin. Rej. 2. Appellant challenges the Examiner’s
objection. See App. Br. 6 – 7. However, the objection relates to a
petitionable matter and not to an appealable matter. See In re Schneider, 481
F.2d 1350, 1356 – 57 (CCPA 1973) and In re Mindick, 371 F.2d 892, 894
(CCPA 1967); see also MANUAL OF PATENT EXAMINING PROCEDURE
(MPEP) § 1201 (8th Ed., Rev. 8, July 2010). Thus, the relief sought by the
Appellant would have been properly presented by a petition to the
Commissioner instead of by appeal to this Board. Accordingly, we will not
consider this issue.
DECISION
The Examiner’s decision to reject claims 1, 4, 5, and 19 – 22 under 35
U.S.C. § 103(a) is reversed.

REVERSED

msc