Ex Parte Jacob et al

Board of Patent Appeals and Interferences

Aug 31, 2011

10386974 (B.P.A.I. Aug. 31, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/386,974 03/12/2003 Stefan Jacob S0193.0001 7908
38881 7590 08/31/2011
DICKSTEIN SHAPIRO LLP
1633 Broadway
NEW YORK, NY 10019
EXAMINER
PANWALKAR, VINEETA S
ART UNIT PAPER NUMBER
2611
MAIL DATE DELIVERY MODE
08/31/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte STEFAN JACOB, MARTIN PEISEL,
and HARALD ZWECK
____________

Appeal 2009-014516
Application 10/386,974
Technology Center 2600
____________

Before GREGORY J. GONSALVES, JEFFREY S. SMITH, and
MICHAEL R. ZECHER, Administrative Patent Judges.

SMITH, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1-14. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

Appeal 2009-014516
Application 10/386,974

2
Invention
Appellants’ invention relates to a delay locked loop (DLL) circuit
having an expanded operating frequency range, achieved by providing
multiple DLLs, each having a different range of operating frequencies. A
selection mechanism selects the DLL with the appropriate operating
frequency range. The output of the selected DLL is used as the output of the
DLL circuit and is fed back to the input of the selected DLL so as to achieve
phase lock with an input signal. Abstract.

Representative Claim
1. A delay locked loop circuit comprising:
a first delay locked loop, the first delay locked
loop having a first operating frequency range;
a second delay locked loop, the second delay
locked loop having a second operating frequency range;
and
a selector, the selector selecting one of the first and
second delay locked loops, wherein the first and second
frequency ranges are different.

Examiner’s Rejections
Claims 1-14 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Taketoshi (US 5,389,898) and Chu (US 6,285,225 B1).

Claim Groupings
In view of Appellants’ arguments in the Appeal Brief, we will decide
the appeal on the basis of claim 1. See 37 C.F.R. § 41.37(c)(1)(vii).
Appeal 2009-014516
Application 10/386,974

3

ISSUE
Would replacing the phase locked loop of Taketoshi with the delay
locked loop of Chu render the circuit of Taketoshi unsatisfactory for its
intended purpose?

FINDINGS OF FACT
Taketoshi
1. Taketoshi teaches a phase locked loop (PLL) formed by a phase
detector, a filter, three selectable voltage controlled oscillators (VCOs), a
multiplexer, and a frequency divider. Each VCO has a different mean
frequency. The multiplexer selects one of the VCOs. If a pulse of a digital
phase difference signal UP indicating that an internal signal is delayed in
phase with respect to a reference signal is output twice in succession, or if a
pulse of a digital phase difference signal DOWN indicating that an internal
signal is advanced in phase with respect to a reference signal is output twice
in succession, a counter makes the multiplexer change its current VCO
selection via a shift register. Accordingly, high-speed PLL pulling is
achievable even if a PLL frequency variable-range is expanded. Abstract;
Fig. 1; col. 4, ll. 20-64.
2. The PLL is applicable to clock generators incorporated into
microprocessors. For example, a PLL is used for the phase lock between
circuit blocks of a microprocessor and for the generation of a multiplication-
frequency clock signal. Col. 1, ll. 7-13.
Appeal 2009-014516
Application 10/386,974

4
Chu
3. Chu teaches that the use of delay locked loop (DLL) circuits
avoids problems associated with the use of PLL circuits. Col. 1, ll. 10-60.

PRINCIPLES OF LAW
If the Examiner’s proposed modification renders the prior art
unsatisfactory for its intended purpose, the Examiner has failed to make a
prima facie case of obviousness. See In re Gordon, 733 F.2d 900, 902 (Fed.
Cir. 1984).
ANALYSIS
Appellants contend that replacing the phase locked loop of Taketoshi
with the delay locked loop of Chu would destroy the intended functionality
of the circuit of Taketoshi, which is to generate a multiplication-frequency
clock signal. App. Br. 4; Reply Br. 3. Appellants contend that the output
signal of the variable delay circuit of the DLL of Chu will always have the
same frequency as the input signal. Therefore, replacing the VCOs of
Taketoshi with the variable delay circuit of Chu does not provide any
possibility of obtaining a multiplication-frequency clock signal. According
to Appellants, the teaching of Chu only applies to circuits where such a
frequency conversion is not required. The teaching of Chu should be
interpreted in the way that a phase locked loop can be replaced by a delay
locked loop if the phase locked loop is only required to adjust or shift the
phase of a signal. Reply Br. 4-7.
Appellants’ arguments are based on the premise that the intended
purpose of the PLL of Taketoshi is to obtain a multiplication-frequency
clock signal having a frequency higher than the frequency of the reference
Appeal 2009-014516
Application 10/386,974

5
signal. However, Taketoshi merely states that this is one example of an
application of a PLL. The intended purpose of Taketoshi is a PLL that can
be used in clock generators incorporated into microprocessors. FF 2.
On page 4 of the Reply Brief, Appellants show Figure 3, which is the
PLL circuit of Taketoshi modified by the teachings of Chu. When the PLL
of Taketoshi is only required to adjust or shift the phase of a signal for a
clock generator incorporated into a microprocessor, then the divider 7 shown
in Figure 3 of the Reply Brief is not needed, and the circuit of Figure 3 will
properly function for Taketoshi’s intended purpose of generating clock
signals.
We sustain the rejection of claim 1 under 35 U.S.C. § 103. Appellants
have not provided arguments for separate patentability of claims 2-14, which
thus fall with claim 1.

CONCLUSION OF LAW
Replacing the phase locked loop of Taketoshi with the delay locked
loop of Chu would not render the circuit of Taketoshi unsatisfactory for its
intended purpose of being used in clock generators incorporated into
microprocessors.

DECISION
The rejection of claims 1-14 under 35 U.S.C. § 103(a) as being
unpatentable over Taketoshi and Chu is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(f).
Appeal 2009-014516
Application 10/386,974

6

AFFIRMED

msc