Ex Parte Iwai et al

Board of Patent Appeals and Interferences

Aug 26, 2010

11147925 (B.P.A.I. Aug. 26, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/147,925 06/08/2005 Tetsuhiro Iwai NGB-35908US1 7276
116 7590 08/26/2010
PEARNE & GORDON LLP
1801 EAST 9TH STREET
SUITE 1200
CLEVELAND, OH 44114-3108
EXAMINER
KACKAR, RAM N
ART UNIT PAPER NUMBER
1716
MAIL DATE DELIVERY MODE
08/26/2010 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
________________

Ex parte TETSUHIRO IWAI
and KIYOSHI ARITA
________________

Appeal 2009-011237
Application 11/147,925
Technology Center 1792
________________

Before MICHAEL P. COLAIANNI, ADRIENE LEPIANE HANLON, and
MARK NAGUMO, Administrative Patent Judges.

NAGUMO, Administrative Patent Judge.

DECISION ON APPEAL1

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.
Appeal 2009-011237
Application 11/147,925

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A. Introduction2
Tetsuhiro Iwai and Kiyoshi Arita (“Iwai”) timely appeal under
35 U.S.C. § 134(a) from the final rejection3 of claims 1-6. We have
jurisdiction under 35 U.S.C. § 6. We AFFIRM.
The 925 Specification explains that after circuits have been formed on
the front surface of a semiconductor substrate 64 (see Figure 2, reproduced
infra), it is desirable to thin the substrate by mechanically grinding the back
surface, and then to plasma etch the back surface to remove layers of
substrate damaged by the grinding. (Spec. 1, 3d para.) The circuits on the
front surface of the substrate are protected by covering them with a
polymeric film 6a. (Id. at para. bridging 1-2, and at para. bridging 5-6.) The
apparatus covered by claim 1 is designed to perform the plasma etching step.
The critical element is this appeal is electrode 3, which acts as the plasma-
generating electrode, as a cold plate to control the temperature of substrate 6,
and—the aspect in contention—as an electrostatic chuck to hold the
substrate in position.

2 Application 11/147,925, Plasma Processing Apparatus and Plasma
Processing Method, filed 8 June 2005, as a Division of an application
filed 17 July 2003 (now U.S. Patent 7,056,831 B2), and claiming the benefit
of a Japanese application filed 18 July 2002. The specification is referred to
as the “925 Specification,” and is cited as “Spec.” The real party in interest
is listed as Matsushita Electric Industrial Co., Ltd. (Appeal Brief,
filed 20 October 2008 (“Br.”), 2.)
3 Office action mailed 1 April 2008 (“Final Rejection”; cited as “FR”).
4 Throughout this opinion, for clarity, labels are presented in bold font,
regardless of their presentation in the original document.
Appeal 2009-011237
Application 11/147,925

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Representative Claim 1 reads:
1. A plasma processing apparatus for plasma processing a
surface of a substrate [6] having an insulating layer [6a] on a
front surface that is accommodated in a processing room,
comprising:
an electrode [3] that is a conductor and has a top
surface that is greater in external size than the
substrate;
cooling means for cooling the electrode; a DC power
section for applying a DC voltage to the electrode to
cause the top surface of the electrode to hold the
substrate by electrostatic absorption; pressure lowering
means for lowering pressure inside the processing
room; a plasma generation gas supply section for
supplying a plasma generation gas to the processing
room; and a radio frequency power section for
generating plasma in the processing room by applying
a radio frequency voltage to the electrode,
wherein the top surface of the electrode has
a top surface central area [A] that is inside a
boundary line [C] that is distant inward by a
prescribed length [E] from an outer periphery of
the substrate [6] and in which the conductor is
exposed, and
a ring shaped top surface outer peripheral
area [B] that surrounds the exposed top surface
central area [A] and in which the conductor is
covered with an insulating coating [3f]
wherein the insulating coating [3f] is
recessed into the top surface outer
peripheral area [B] of the conductor such
that a top surface of the insulating coating is
substantially level with the top surface outer
peripheral area of the conductor.
(Claims App., Br. 16; indentation, paragraphing, bracketed labels, and
emphasis added.)
Appeal 2009-011237
Application 11/147,925

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The electrode and the substrate are shown in 925 Specification
Figure 2, which is reproduced below:
{Figure 2}

{Figure 2 is said to show an electrode assembly}
The critical features of electrode 3 are that the upper surface 3g is
larger than electrode 6; that the central area A is conductive and exposed to
corresponding insulated area D of silicon wafer 6; that peripheral ring B,
which is covered by insulating coat 3f, is wide enough that it overlaps
peripheral ring E of substrate 6, when substrate 6 is positioned
concentrically on electrode 3; and that the surface of insulating coat 3f is at
substantially the same level as the rest of the surface 3g of electrode 3, so
that substrate 6 lies flat on the electrode. The 925 Specification states that
“[t]he silicon wafer 6 is electrostatically absorbed on the top surface central
Appeal 2009-011237
Application 11/147,925

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area A by mainly utilizing the central portion D of the protective film 6a5 as
a dielectric for electrostatic absorption.” (Spec. 11, last para.) As a result
of shielding by the silicon wafer 6 and the insulating layer 3f, the conductive
electrode 6 is said to be insulated from the plasma, “whereby an abnormal
discharge is prevented.” (Spec. 10, 1st full para.)
The Examiner has maintained the following grounds of rejection:6
A. Claims 1-5 stand rejected under 35 U.S.C. § 103(a) in view of
the combined teachings of Kakehi,7 Shufflebotham,8 and
Kanai.9
B. Claim 6 stands rejected under 35 U.S.C. § 103(a) in view of the
combined teachings of Kakehi, Shufflebotham, and Kanai, and
Kawakami.10
Iwai argues that the Examiner failed to establish a prima facie case of
obviousness because the references do not teach or suggest all of the

5 According to the 925 Specification, the film is made of an insulative resin
such as polyolefin, polyimide, or polyethylene terephthalate and has a
thickness of about 100 mm.” (Spec. 6, ll. 1-3.) The reported thickness is
surely in error, but we are unable to say how thick a film Iwai intended.
6 Examiner’s Answer mailed 6 January 2009. (“Ans.”)
7 Yutaka Kakehi et al., Method and Apparatus for Controlling Sample
Temperature, U.S. Patent 4,565,601 (1986).
8 Paul Kevin Shufflebotham and Michael S. Barns, Electrostatic Clamping
Method and Apparatus for Dielectric Workpieces in Vacuum Processors,
U.S. Patent 5,847,918 (1998).
9 Hideki Kanai et al., Plasma Processing Apparatus and Plasma Processing
Method, U.S. Patent 5,792,376 (1998).
10 Satoru Kawakami et al., Plasma Treatment Apparatus, U.S. Patent
5,542,559 (1996).
Appeal 2009-011237
Application 11/147,925

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electrode structures required.11 In particular, according to Iwai, Kakehi
teaches that the surface of electrode 26 is coated with an insulating film, so
Kakehi does not teach or suggest uncoated central area A. (Br. 9, 2d para.)
Moreover, Iwai argues that Kakehi does not teach peripheral ring region B
that is insulated with a coating that is substantially level with the top surface
of the outer peripheral area of the conductor.12 (Id. at 10, 1st full para.)
Shufflebotham, according to Iwai, does not cure these deficiencies because
Shufflebotham’s electrode 36 does not have a larger top surface than
substrate 32, and because there is no ring-shaped outer peripheral area of the
electrode that is covered by an insulating coating, recessed or otherwise.
Iwai argues that the recessed insulator 51, shown in Figure 5 of Kanai, does
not cure the deficiencies of Shufflebotham because that recessed insulator is
not taught or suggested to be recessed into the outer peripheral area of the
conductor. (Id. at 11, penultimate para.) Moreover, Iwai argues, the
teachings of Kakehi cannot be combined with those of Kanai because, in
Iwai’s view, the substrate mounting region of Kanai is expressly taught to be

11 Because Iwai does not dispute that the other limitations of claim 1 are
taught or obvious in view of the applied references, we shall not address
them in this Opinion.
12 The recitation “a top surface of the insulating coating is substantially level
with the top surface outer peripheral area of the conductor” has been treated
by Iwai, without objection from the Examiner, as meaning that the top
surface of the insulating coating is level with the original top surface of the
outer peripheral area of the conductor (i.e., prior to formation of the
insulating layer). In other words, that the top surface (ignoring holes) is
everywhere level, as shown in Figure 2. The actual claim language is
nonsensical because the insulating coating is recessed into, and therefore
overlies the top surface of the conductor.
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Application 11/147,925

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free of an insulative covering, and the proposed modification of Kanai
would change the principle of operation of Kanai’s invention. (Id. at para.
bridging 12-13.)
Iwai argues that Kawakami merely teaches a top surface with
absorption holes connected to a vacuum absorption pump and does not cure
the deficiencies of Kakehi, Shufflebotham, and Kanai. (Br. 14.)
In the Examiner’s Answer, the Examiner corrects several
misstatements made in the final rejection regarding the teachings of Kakehi
and Shufflebotham. The Examiner finds that Kakehi describes an
embodiment of a plasma processing apparatus with the electrode assembly
shown in Figure 7, which is reproduced below.

{Kakehi Figure 7 is said to show an electrode assembly}
The Examiner finds that electrode 26 is a conductor having a top surface
larger than substrate 50, and that insulating coating 110′ covers a peripheral
area 26′ of the electrode, leaving an uncoated central area 26″ that is inside a
boundary line that is distant inward by a prescribed length from an outer
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periphery of the substrate 50. (Ans. 4, 1st full para.) The Examiner finds
further that insulating coating 110′ is recessed in the top surface of the
electrode and is partially covered by the substrate. (Id.) In other words, as
shown in Figure 7, substrate 50 overhangs central area 26″ of the electrode.
The Examiner argues that Kakehi teaches that, for electrostatic attraction, an
insulating coating underneath the substrate is equivalent to coating 60 [not
shown but present] on electrode 26. (Id., 2d full para, citing Kakehi, col. 9,
ll. 20-30.) In this regard, we note that Kakehi states that “[t]he same effect
[i.e., electrostatic attraction between the substrate and the electrode] is also
obtained by coating the substrate with a highly dielectric polymer resin such
as polyimid resin.” (Kakehi, col. 9, ll. 28-30.) The Examiner concludes that
it would have been obvious to obtain an equivalent electrostatic attraction
between substrate 50 and the central area 26″ of the electrode by providing a
polymer resin coating on the underside of the substrate rather than on the top
surface of the electrode. (Ans. 4, 3d full para.) The Examiner also argues
that Kakehi “suggest[s] optimization of insulating layer height (Col 8
lines 18-31) but do[es] not explicitly disclose that a top surface of the
insulating coating is substantially level with the top surface outer peripheral
area of the conductor.” (Id. at 4, last para.)
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Application 11/147,925

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The Examiner finds that Shufflebotham describes a plasma processing
chamber in which, in the embodiment depicted in Figure 2, shown below,

{Shufflebotham Figure 2 is said to show an electrode assembly}
dielectric substrate 32 is electrostatically held to electrode 36 and to a
peripheral insulator 43 that is surface flush with the exposed electrode
surface. (Ans. 5, 3d full para.)
The Examiner argues that Shufflebotham shows that the alignment of
the substrate on the conductor is not critical for electrostatic attraction, and
that therefore it would have been obvious to adjust the thickness of
insulating region 110′ of the electrode shown in Kakehi Figure 7 to be level
with the top of conductor 26′ in order to accommodate larger substrates
while still protecting the electrode from exposure to plasma. (Ans. 5, 4th
and 5th paras.)
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Application 11/147,925

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The Examiner also finds that Kanai describes a plasma processing
chamber in which an insulating surface is recessed into a conductor.
(Ans. 5-6.)
In the Reply,13 Iwai only reiterates the arguments that Kanai does not
teach a recessed peripheral insulating layer and that the combination of
Kakehi and Kanai is improper. (Reply 2-3.)
B. Discussion
As the Appellant, Iwai bears the procedural burden of showing
harmful error in the Examiner’s rejections. See, e.g., Shinseki v. Sanders,
129 S.Ct. 1696, 1706 (2009) (citations omitted) (“Lower court cases make
clear that courts have correlated review of ordinary administrative
proceedings to appellate review of civil cases in this respect. . . . [T]he party
seeking reversal normally must explain why the erroneous ruling caused
harm.”) See also, In re Chapman, 595 F.3d 1330, 1338 (Fed. Cir. 2010)
(discussing the role of harmless error in appeals from decisions of the Board
of Patent Appeals and Interferences (“Board”)). Arguments not timely made
have been waived. 37 C.F.R. § 41.37(c)(1)(vii) (second sentence); see also
In re Hyatt, 211 F.3d 1367, 1373 (Fed. Cir. 2000) (an argument not first
raised in the brief to the Board is waived on appeal).
The preponderance of the evidence indicates that Kakehi teaches that
the location of insulating film 60 on the lower surface of substrate 50 was
considered to be equivalent, and thus would have been an obvious variation,

13 Reply Brief filed 4 March 2009 (“Reply”).
Appeal 2009-011237
Application 11/147,925

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to placing the insulating film on upper surface of electrode 26 in order to
obtain electrostatic binding of the substrate to the electrode. In any event,
Iwai has not contested, in its Reply, the Examiner’s finding to that effect, so
the issue has been waived for the present appeal. Iwai’s challenge to the
Examiner’s findings that Kakehi teaches all the limitations of the electrode
but for the top surface of the insulating peripheral ring being substantially
level with the top surface of the conductor (Br. 9-11) are not persuasive of
harmful error in the Examiner’s position as set out in the Examiner’s
Answer. The upper surface of electrode 26 is indisputably larger than
substrate 50, and the peripheral ring defined by insulator 110′ is shown as
being covered in part by the outer edge of substrate 50.
As for the “substantially level” limitation, Iwai has not challenged the
Examiner’s finding that Kakehi teaches that the relative heights of
insulator 110′ and the central region 26″ of the electrode can be adjusted.
Nor has Iwai challenged the Examiner’s findings that Shufflebotham
indicates that the placement of a substrate on an electrostatic chuck is not
critical, and that a peripheral insulator may be flush with the electrode, thus
allowing the substrate to extend beyond the conductive area of the
electrode. These findings support the Examiner’s holding that it would have
been obvious to adjust the height of the central region 26″ of the electrode to
be substantially level with the height of the peripheral insulating region 110′
in order to accommodate large substrates. The Examiner’s reliance on
Kanai is thus seen to be cumulative. Therefore, even if erroneous, that
reliance was harmless.
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The preponderance of the evidence indicates that a person having
ordinary skill in the art would have had a reasonable expectation that the
electrode shown in Kakehi Figure 7, so modified, would have performed the
electrostatic binding function as well as the other functions, and that the
electrode would continue to be protected against abnormal discharge with
the plasma. Accordingly, we conclude that Iwai has not shown harmful
error in the Examiner’s rejection of claim 1.
As Iwai does not criticize the rejection of claim 6 except to argue that
Kawakami does not cure the alleged defects of Kakehi, Shufflebotham, and
Kanai, we conclude that harmful error has not been shown regarding that
rejection as well.
C. Order
We AFFIRM the rejection of claims 1-5 under 35 U.S.C. § 103(a) in
view of the combined teachings of Kakehi, Shufflebotham, and Kanai.
We AFFIRM the rejection of claim 6 under 35 U.S.C. § 103(a) in
view of the combined teachings of Kakehi, Shufflebotham, and Kanai, and
Kawakami.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED

cam

Appeal 2009-011237
Application 11/147,925

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PEARNE & GORDON LLP
1801 EAST 9TH STREET
SUITE 1200
CLEVELAND, OH 44114-3108