Ex Parte Ito

Patent Trial and Appeal Board

Sep 21, 2012

10419151 (P.T.A.B. Sep. 21, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte YOSHIYUKI ITO
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Appeal 2010-005436
Application 10/419,151
Technology Center 2100
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Before JOHN A. JEFFERY, JEFFREY S. SMITH, and
STANLEY M. WEINBERG, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-8, 11, 13, 14, and 17-23. We have jurisdiction under
35 U.S.C. § 6(b). We affirm.

STATEMENT OF THE CASE
Appellant’s invention simultaneously emulates and simulates a target
device using hardware and software, respectively. See generally Abstract;
Spec. ¶¶ 20-29. Claim 1 is illustrative:
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1. A simulation method for simulating a target device with fixed and
unfixed design specifications, the method comprising:
emulating a part of a circuit information of a target device to emulate
said fixed design specification by an emulation subject circuit constructed by
a rewritable hardware;
simulating a remaining part of the circuit information of said target
device to simulate said unfixed design specification, wherein a software
program represents said unfixed design specification, by a partial circuit
process substitute section constructed by software; and
communicating data between said emulation subject circuit and said
partial process substitute section, wherein a result of said simulating and said
emulating is stored in one of a host computer and a storage medium, or
displayed on a display, and said emulating and said simulating are
performed simultaneously.

THE REJECTION
The Examiner rejected claims 1-8, 11, 13, 14, and 17-23 under 35
U.S.C. § 103(a) as unpatentable over William D. Bishop & Wayne M.
Loucks, A Heterogeneous Environment for Hardware/Software
Cosimulation, 30TH ANN. SIMULATION SYMP. 14 (1997) (“Bishop”) and Jay
K. Adams & Donald E. Thomas, The Design of Mixed Hardware/Software
Systems, 33D ANN. DESIGN AUTOMATION CONF. 515 (1996) (“Adams”).
Ans. 3-6.1

CONTENTIONS
The Examiner finds that Bishop’s target device simulation method has
every recited feature of representative claim 1 except for system partitioning
according to fixed and unfixed specifications, but cites Adams as teaching

1 Throughout this opinion, we refer to the Appeal Brief filed July 15, 2009
(supplemented September 4, 2009) and the Examiner’s Answer mailed
November 30, 2009.
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this feature in concluding that the claim would have been obvious. Ans. 3-4,
6-10.
Appellant argues that the cited prior art does not teach or suggest
simultaneous emulation and simulation, let alone doing so with respect to
fixed and unfixed design specifications, respectively, as claimed. Br. 9-12.
According to Appellant, Bishop does not synchronize events between
hardware and software simultaneously. Br. 10. Although Appellant
acknowledges that Adams partitions hardware and software functionality,
Appellant contends that these functions are not used to simulate a target
device and, as such, Adams is not combinable with Bishop. Br. 11-12.
Appellant also argues limitations of claims 13 and 20 summarized below.

ISSUES
I. Under § 103, has the Examiner erred by finding that Bishop and
Adams collectively would have taught or suggested:
(1) simultaneously (a) emulating part of a target device’s circuit
information to emulate a fixed design specification by an emulation subject
circuit constructed by rewritable hardware, and (b) simulating a remaining
part of the circuit information to simulate an unfixed design specification by
a partial circuit process substitute section constructed by software as recited
in claim 1?
(2) part of the target device’s circuit information having a fixed design
specification, and the remaining part of the information having an unfixed
design specification as recited in claim 13?
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(3) when a new design specification is fixed, part of the circuit
information is increased based on the new specification as recited in claim
20?
II. Is the Examiner’s reason to combine the teachings of Bishop and
Adams supported by articulated reasoning with some rational underpinning
to justify the Examiner’s obviousness conclusion?

ANALYSIS
Claims 1-8, 11, 14, 17-19, and 21-23
We sustain the Examiner’s obviousness rejection of representative
claim 1 for the reasons indicated by the Examiner. Ans. 3-4, 6-10. As the
Examiner indicates, Bishop’s system simulates some of an application’s
subsystems using reconfigurable hardware, while the remainder of the
subsystems are simulated via software. Ans. 7 (citing Bishop Abstract).
Notably, Bishop refers to this co-simulation2 in connection with
synchronous parallel simulation (Bishop 17-18, § 3.2): a term that at least
suggests simultaneous hardware/software simulation, particularly in view of
Appellant’s characterizing this feature in connection with parallel processing
as the Examiner indicates. Ans. 6 (quoting Spec. ¶ 61).
The Examiner’s reference to Bishop’s handshaking and
synchronization between simulation software and hardware in Figure 2 as
teaching the recited simultaneous emulation and simulation is also well
taken and not persuasively rebutted. Ans. 7-8 (citing Bishop Fig. 2). As

2 Although Bishop does not hyphenate this term, we nonetheless hyphenate
it for clarity and proper grammatical form. Accord Adams § 3.1
(hyphenating “co-simulation”).
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shown in that figure, both software and hardware processing of I/O read
requests associated with the simulation hardware and software occurs
simultaneously at least from time t2 to t3. See Bishop 18, § 3.2; Fig. 2. As
such, we see no error in the Examiner’s position that this concurrence
between the respective hardware and software simulation functions at least
suggests simultaneous emulation and simulation as claimed. Ans. 7-8.
Appellant’s contention that Bishop synchronizes events within either
hardware or software, but does not synchronize events between them
simultaneously (Br. 10) is unavailing and, in any event, does not
persuasively rebut the Examiner’s reliance on the handshaking and
synchronization functions in Bishop’s Figure 2 noted above.
Nor are we persuaded of error in the Examiner’s reliance on Adams
merely to show that software implementations are desirable in terms of their
“modifiability,” such that functions and algorithms are easily changed. Ans.
9-10 (citing Adams § 3.3). This teaching at least suggests the advantage of
simulating a target device as in Bishop according to an “unfixed” (i.e.,
changeable) design specification via software, particularly since (1) Adams
pertains to hardware/software co-simulation (Adams § 3.1) and
concurrency,3 and (2) Bishop notes the disadvantages of hardware emulation
including, among other things, long turn-around times for design changes.
Bishop 14-15, § 1. We therefore find the Examiner’s reason to combine the
teachings of Bishop and Adams supported by articulated reasoning with

3 See Adams § 3.3 (“If the software and hardware components run
asynchronously, the best system performance can be achieved by exploiting
concurrency among them.”).
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some rational underpinning to justify the Examiner’s obviousness
conclusion.
We are therefore not persuaded that the Examiner erred in rejecting
representative claim 1, and claims 2-8, 11, 14, 17-19, and 21-23 not
separately argued with particularity.

Claim 13
For similar reasons, we also sustain the Examiner’s rejection of claim
13 which recites part of the target device’s circuit information has a fixed
design specification, and the remaining part of the information has an
unfixed design specification. Even assuming, without deciding, that
Bishop’s output switched buffer model4 in Figure 4 does not explicitly
disclose a fixed specification as Appellant contends (Br. 12), this model is
nevertheless associated with a co-simulation application in Bishop that uses
features commensurate with those noted above. See Bishop 20, § 5.
Appellant’s arguments therefore do not persuasively rebut the Examiner’s
position based on the collective teachings of Bishop and Adams regarding
simulating fixed and unfixed design specifications via hardware and
software respectively noted above.
We are therefore not persuaded that the Examiner erred in rejecting
claim 13.

4 Although Appellant characterizes this feature as an “output buffered switch
module” (Br. 12), Bishop refers to it as an “output buffered switch model.”
Bishop 20-21, §§ 5-5.1; Fig. 4 (emphases added).
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Claim 20
We also sustain the Examiner’s rejection of claim 20 (Ans. 5, 20)
reciting that when a new design specification is fixed, part of the circuit
information is increased based on the new specification. Apart from
summarily asserting that the cited prior art fails to disclose the recited
feature (Br. 12), Appellant does not explain why this is the case, let alone
particularly show error in the Examiner’s rejection. See 37 C.F.R. §
41.37(c)(1)(vii) (noting that an argument that merely points out what a claim
recites is unpersuasive). Accord In re Lovin, 652 F.3d 1349, 1357 (Fed. Cir.
2011) (“[T]he Board reasonably interpreted Rule 41.37 to require more
substantive arguments in an appeal brief than a mere recitation of the claim
elements and a naked assertion that the corresponding elements were not
found in the prior art.”).
We are therefore not persuaded that the Examiner erred in rejecting
claim 20.

CONCLUSION
The Examiner did not err in rejecting claims 1-8, 11, 13, 14, and 17-
23 under § 103.

ORDER
The Examiner’s decision rejecting claims 1-8, 11, 13, 14, and 17-23 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

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AFFIRMED

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