Ex Parte ISLOORKAR

Patent Trials and Appeals Board

Mar 19, 2019

13705318 - (D) (P.T.A.B. Mar. 19, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/705,318 12/05/2012
73459 7590 03/21/2019
NIXON & V ANDERHYE, P.C.
901 NORTH GLEBE ROAD, 11 TH FLOOR
ARLINGTON, VA 22203
FIRST NAMED INVENTOR
Nitin ISLOORKAR
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
SCS-550-1564 8967
EXAMINER
WARREN, TRACY A
ART UNIT PAPER NUMBER
2131
NOTIFICATION DATE DELIVERY MODE
03/21/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PTOMAIL@nixonvan.com
pair_nixon@firsttofile.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte NITIN ISLOOKRKAR
Appeal2018-004592
Application 13/705,318 1
Technology Center 2100
Before LARRY J. HUME, CATHERINE SHIANG, and
JASON J. CHUNG, Administrative Patent Judges.
CHUNG, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) of the Final
Rejection of claims 1, 3-10, and 12-18. 2 We have jurisdiction under
35 U.S.C. § 6(b).
We reverse.
INVENTION
The invention is directed to data processing and in particular to the
translations of virtual to physical addresses within data processing systems.
Spec. 2:4--5. Claim 1 is illustrative of the invention and is reproduced
below:
1 According to Appellant, ARM Limited is the real party in interest. App.
Br. 3.
2 Claims 2 and 11 are canceled. Final Act. 2.
Appeal2018-004592
Application 13/705,318
1. A data processing apparatus comprising:
at least one initiator device for issuing transactions,
a hierarchical memory system comprising a plurality of
caches and a memory and memory access control circuitry,
said initiator device being configured to identify storage
locations using virtual addresses,
said hierarchical memory system being configured to
store data using physical addresses,
said memory access control circuitry being configured to
control virtual address to physical address translations; wherein:
said plurality of caches comprise a first cache and a
second cache;
said first cache being configured to store a plurality of
address translations of virtual to physical addresses that said
initiator device has requested;
said second cache being configured to store a plurality of
address translations of virtual to physical addresses that it is
predicted that said initiator device will subsequently request;
said first and second cache are arranged in parallel with
each other such that said first cache can be accessed during an
access cycle in response to receipt of a request for an address
translation from said initiator device, and said second cache can
be accessed during said same access cycle in response to receipt
of said request for said address translation from said initiator
device; and
said memory access control circuitry is configured, in
response to receipt of said request for said address translation
from said initiator device, to look for said translation in said
first cache and said second cache and in response to said
requested translation not being present:
to retrieve said translation from a lower
hierarchical data store and
to retrieve a translation for a predicted
subsequently required virtual address while accessing
said lower hierarchical data store and
to update said first cache with said retrieved
translation and said second cache with said retrieved
predicted subsequently required translation at a same
time.
2
Appeal2018-004592
Application 13/705,318
REJECTIONS AT ISSUE
Claims 1, 3, 12, 13, and 18 stand rejected under 35 U.S.C. §§ I02(b)/
I03(a) as being anticipated or unpatentable over Bhattacharjee (Abhishek
Bhattacharjee et al., Inter-Core Cooperative TLB Prefetchers for Chip
Multiprocessors, ASPLOS '10 (2010) ("Bhattacharjee")). Ans. 7-16.
Claims 4, 6, 7, and 14--16 stand rejected under 35 U.S.C. § I03(a) as
being unpatentable over the combination of Bhattacharjee, Gupta (US
2013/0227245 Al; filed Feb. 28, 2012), and Applicant's Admitted Prior Art.
Ans. 16-23. 3
Claim 5 stands rejected under 35 U.S.C. § I03(a) as being
unpatentable over the combination of Bhattacharjee and Lais (US
2006/0101209 Al; published May 11, 2006). Ans. 23-24.
Claim 8 stands rejected under 35 U.S.C. § I03(a) as being
unpatentable over the combination of Bhattacharjee and Torres (Gabriel
Torres, How the Cache Memory Works: n-Way Set Associative Cache,
Hardware Secrets (Sept. 12, 2007), https://www.hardwaresecrets.com/how-
the-cache-memory-works/8/ ("Torres")). Ans. 24--25.
Claim 9 stands rejected under 35 U.S.C. § I03(a) as being
unpatentable over the combination of Bhattacharjee, Applicant's Admitted
Prior Art, and Murayama (US 2010/0011170 Al; published Jan. 14, 2010).
Ans. 25-26.
3 The Examiner includes claim 9 in the heading. However, claim 9 stands
rejected over the combination of Bhattacharjee, Applicant's Admitted Prior
Art, and Murayama (US 2010/0011170; published Jan. 14, 2010). Ans. 25-
26. We, therefore, interpret the Examiner's inclusion of claim 9 in this
heading as a typographical error.
3
Appeal2018-004592
Application 13/705,318
Claims 10 and 17 stand rejected under 35 U.S.C. § I03(a) as being
unpatentable over the combination of Bhattacharjee and Day (US
2007/0113044 Al; published May 17, 2007). Ans. 27-31.
ANALYSIS
Claims 1 and 18 recite ( emphasis added):
said memory access control circuitry is configured, in
response to receipt of said request for said address translation
from said initiator device, to look for said translation in said
first cache and said second cache and in response to said
requested translation not being present:
to retrieve said translation from a lower hierarchical data
store and
to retrieve a translation for a predicted subsequently
required virtual address while accessing said lower hierarchical
data store and
to update said first cache with said retrieved translation
and said second cache with said retrieved predicted
subsequently required translation at a same time.
Claim 12 recites similar limitations. The Examiner concludes
claims 1 and 18 do not recite explicitly "to look for said translation in said
first cache and said second cache and in response to said requested
translation not being present [in said first cache or said second cache]" and
Appellant acknowledges this because they have to bracket this limitation not
recited in claims 1 and 18. Ans. 35-36; Final Act. 31-32. Moreover, the
Examiner concludes the claims do not require what is recited in the brackets
above. Ans. 35-36; Final Act. 31-32.
Appellant argues claims 1 and 18 recite the bracketed portions below
because claims 1 and 18 recite "to lookfor said translation in said first
cache and said second cache and in response to said requested translation
4
Appeal2018-004592
Application 13/705,318
not being present ... " (emphasis added). App. Br. 16-17; Reply Br. 3--4.
We agree with Appellant.
Claims 1 and 18 explicitly recite "to look for said translation in said
first cache and said second cache and in response to said requested
translation not being present ... " ( emphasis added). Claim 12 recites
similar limitations. Significantly, the Examiner concludes the claims do not
require what is recited in the brackets above and does not address this
limitation with a pinpoint citation to a reference. Ans. 35-36; Final
Act. 31-32. By interpreting claims 1 and 18 as not requiring the bracketed
portions above, the Examiner improperly reads "to look for said translation
in said first cache and said second cache and in response to said requested
translation not being present ... " ( emphasis added) out of claims 1 and 18
such that the Examiner is taking claims 1 and 18 out of context improperly.
Accordingly, we do not sustain the Examiner's rejection of:
(1) independent claims 1, 12, and 18; and (2) dependent claims 3-10 and
13-17 under 35 U.S.C. §§ 102(b) and 103(a).
DECISION
We reverse the Examiner's decision rejecting claims 1, 3-10, and 12-
18 under 35 U.S.C. §§ 102(b) and 103(a).
REVERSED
5