Ex Parte Ingram et al

Board of Patent Appeals and Interferences

Feb 28, 2012

11173156 (B.P.A.I. Feb. 28, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte GRAEME LESLIE INGRAM and IAN JAMES QUINN
____________

Appeal 2010-007678
Application 11/173,156
Technology Center 2100
____________

Before MAHSHID D. SAADAT, KALYAN K. DESHPANDE,
and JASON V. MORGAN, Administrative Patent Judges.

SAADAT, Administrative Patent Judge.

DECISION ON APPEAL1

1 An Oral Hearing for this appeal was held on February 23, 2012.
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Application 11/173,156

2
Appellants appeal under 35 U.S.C. § 134(a) from the rejection of
claims 1-9, 15-27, and 33-35. Claims 10-14 and 28-32 are objected to as
being dependent upon a rejected base claim, but would be allowable if
rewritten in independent form including all of the limitations of the base
claim and any intervening claims. We have jurisdiction under 35 U.S.C.
§ 6(b).
We affirm.

STATEMENT OF THE CASE
Introduction
Appellants’ invention relates to a memory controller operable to
control a memory for being operable in a plurality of modes (see Spec. 1:18-
28).
Exemplary independent claim 1 reads as follows:
1. A memory controller for controlling a memory,
said memory operable in a plurality of communication modes,
said memory controller comprising:
memory interface logic configured to interact with said
memory in each of said plurality of communication modes; and
memory mode change logic, in response to a memory
mode change request instruction specifying a predetermined
one said plurality of communication modes being issued by said
memory interface logic to said memory, configured to request
said memory interface logic to be configured to interact with
said memory in said predetermined one of said plurality of
communication modes and to prevent interaction between said
memory interface logic and said memory until said memory
interface logic confirms that it is configured to interact with
said memory in said predetermined one of said plurality of
communication modes.
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Rejection
The Examiner rejected claims 1-9, 15-27, and 33-35 under 35 U.S.C.
§ 102(e) as being anticipated by Chang (US 2005/0081002 A1).
Appellants’ Contentions
With respect to independent claims 1, 18, and 19, Appellants contend
that Chang does not support a finding of anticipation because the cited
portions of the reference, in paragraphs 35 and 65, describe the operational
mode of a synchronous dynamic random access memory (SDRAM), instead
of the claimed “plurality of communication modes” (App. Br. 7-8).
Appellants specifically assert:
Appellants’ claim specifically recites “communication
modes” and this term is well known to those of ordinary skill in
the art. Moreover, examples of such “communication modes”
are given in Appellants’ specification at page 10, lines 25-30,
which indicates “synchronous mode” and “asynchronous
mode.” The Examiner’s attention is directed to Appellants’
specification, page 10, lines 16-30, in which it is discussed that
the interface logic supports communication with memory
devices in “any of a variety of different modes” and the next
paragraph, lines 25-30, discuss that the memory device can
communicate in the “synchronous mode” or in the
“asynchronous mode.”
(App. Br. 8).
The Examiner’s reference to Chang’s paragraphs 35 and
65 in line 5 of page 3 of the Official Action, as noted above, is a
vague reference to possible support in the Chang reference for
the claimed “memory interface logic.” However, there is no
identified portion of Chang that teaches that the memory
controller changes its form of communication. As noted, the
modes referenced in Chang are modes of operation of a
memory only. There is no identification by the Examiner of any
communication mode disclosed in Chang and therefore there
can be no memory interface logic which is “configured to
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interact with said memory in each of said plurality of
communication modes” (emphasis added).

(App. Br. 9).
Appellants further contend that Chang fails to teach the recited
memory mode change logic configured to interact with the memory
and configured to prevent interaction based on the alleged lack of
disclosure of the term “communication modes” (App. Br. 10-13).

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
contentions that the Examiner has erred. We disagree with Appellants’
conclusions. We adopt as our own (1) the findings and reasons set forth by
the Examiner in the action from which this appeal is taken and (2) the
reasons set forth by the Examiner in the Examiner’s Answer in response to
Appellants’ Appeal Brief. However, we highlight and address specific
findings and arguments regarding claim 1 for emphasis as follows.
We find that the Examiner, giving the claim its broadest reasonable
interpretation consistent with the Specification, In re Morris, 127 F.3d 1048,
1054 (Fed. Cir. 1997), properly relies on paragraphs 35 and 65 of Chang for
disclosing the claimed memory controller for controlling a memory operable
in a plurality of communication modes (Ans. 3-4). The relied-on portions of
Chang describe that the memory controller 31 transmits a control signal 36
to the memory device 32 in the form of a command for determining the
mode of an SDRAM, such as idle, row active, write/read, and pre-charge
(see Chang, ¶ [0035] – [0036]). Additionally, Chang discloses that changing
the mode of the memory device 32 enables data transactions between the
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CPU core 10 and the memory device 32 (¶ [0034]). Therefore, Chang’s
disclosure implies that each of these modes, while described as operational
modes, affect the data transaction or the way communication with the
memory device takes place.
Contrary to Appellants’ position (Reply Br. 2), this interpretation is
consistent with Appellants’ Specification (see Spec. 10:16-24 and 11:9-18)
which describes that “[t]he interface logic 130 supports communication with
the memory devices 90, 100, 110, 120 in any of a variety of different
modes.” However, while Appellants’ Specification at page 10, lines 25-30,
mentions “synchronous mode” and “asynchronous mode,” the Specification
provides no express definition for the claim term “communication modes.”
Appellants’ Specification merely describes that the logic 130 communicates
with the memory device while the memory device is “in any of a variety of
modes” (Spec. 10:17-19). In that regard, Chang discloses data transaction
based on the mode determined by the memory controller 31 connected to the
memory device 32 while the memory device may be in any of the plurality
of modes such as idle or active when the data transactions between the CPU
and the memory 32 is enabled. Beyond conclusory assertions and citations
to the Chang reference, Appellants provide absolutely no reasoning or
evidence to support the assertion that one of ordinary skill in the art would
find a more narrow construction of the term “communication modes” than
the construction given to the term by the Examiner.2

2 In the event of further prosecution, the Examiner is invited to consider
claim 1 for compliance with the provisions of 35 U.S.C. § 112, first and
second paragraphs.
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Furthermore, the Examiner sets forth additional reasoning and
response to Appellants’ contentions to explain why Chang’s memory modes
can be considered “operational modes” (Ans. 8). As stated by the Examiner
(id.), each of the disclosed modes is determined by a command included in
the control signal from the memory controller 31 similar to the direct
command disclosed in Appellants’ Specification which “may also contain
instructions for the memory device as well indicating a required mode of
operation” (see Spec. 11:11-12). Appellants provide no convincing response
to the Examiner’s additional reasoning and assert that page 11 of the
Specification describes “a further direct command” that provides
instructions indicating a required mode of operation (Reply Br. 3). We
disagree with Appellants and note that the description of Appellants’ Figure
2 (see Spec. 10:19-24) also indicate that the parameters provided in the
interface configuration registers 140, 150, 160, and 170 configure or
program the interface logic 130 to support the particular mode of operation
of the memory device. Therefore, nothing in the record suggests that the
Examiner’s interpretation of “communication mode” is unreasonable or
inconsistent with the Specification.

CONCLUSION
On the record before us, we conclude that, because the reference
teaches all the claim limitations, the Examiner has not erred in rejecting
claims 1, 18, and 19 as being anticipated by Chang. Therefore, we sustain
the 35 U.S.C. § 102 rejection of claims 1, 18, and 19, and of claims 2-9, 15-
17, 20-27, and 33-35 dependent thereon, which are not separately argued.

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DECISION
The Examiner’s decision rejecting claims 1-9, 15-27, and 33-35 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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