Ex Parte Ingle et alDownload PDFPatent Trial and Appeal BoardJan 14, 201512146657 (P.T.A.B. Jan. 14, 2015) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________________ Ex parte AJAY ANANT INGLE and CHRISTOPHER EDWARD KOOB ____________________ Appeal 2012-009546 Application 12/146,657 Technology Center 2800 ____________________ Before JEFFREY S. SMITH, CATHERINE SHIANG, and WILLIAM M. FINK, Administrative Patent Judges. FINK, Administrative Patent Judge. DECISION ON APPEAL Appellants1 seek our review under 35 U.S.C. § 134(a) of the Examiner’s final rejection of claims 1–23, 25–30, 32–37, and 39–43. We have jurisdiction under 35 U.S.C. § 6(b). We affirm-in-part. 1 According to Appellants, the real party in interest is Qualcomm, Incorporated. (App. Br. 3.) Appeal 2012-009546 Application 12/146,657 2 STATEMENT OF THE CASE Appellants’ Invention Appellants’ invention relates to a memory management unit. (Spec., Abstract.)2 More specifically, Appellants’ invention is directed to a memory management unit that stores a bit associated with a physical address range and indicating one of a plurality of interfaces. (Id.) Claims on Appeal Claims 1, 9, 17, 23, 30, and 37 are the independent claims on appeal. Claims 1, 4, and 17 are illustrative of Appellants’ invention and are reproduced below: 1. A translation lookaside buffer (TLB) comprising: a storage module configured to store a bit indicating one interface of a plurality of interfaces, the bit being associated with a physical address range; and a logic circuit configured to route a physical address within the physical address range to the one of the plurality of interfaces based on the bit. 4. The TLB of claim 1, wherein the TLB has a size and the storage module is configured to receive the bit from a second TLB having a larger size than the TLB size. 17. A method comprising: receiving a transaction request from a processor thread, the transaction request comprising a virtual address; 2 Our decision refers to Appellants’ Appeal Brief filed January 30, 2012 (“App. Br.”); the Examiner’s Answer mailed April 12, 2012 (“Ans.”); Appellants’ Reply Brief filed June 8, 2012 (“Reply Br.”); the Final Office Action mailed September 2, 2011 (“Final Act.”); and the original Specification filed June 26, 2008 (“Spec.”). Appeal 2012-009546 Application 12/146,657 3 identifying a physical address corresponding to the virtual address; decoding the physical address using system-on-a-chip (SOC) memory map strappings to provide a bit identifying one interface of a plurality of interfaces, the bit being associated with a physical address range; storing the physical address and the bit in a micro translation lookaside buffer (µTLB); identifying the virtual address in the µTLB; and routing the physical address to the one interface of the plurality of interfaces based on the bit, the physical address being within the physical address range. Examiner’s Rejections Claims 1–7, 9–15, 17–23, 25–30, 32–37, and 39–43 stand rejected under 35 U.S.C. § 102(b) as being anticipated by Vishin (US 5,860,146, January 12, 1999). (Ans. 3–17.) Claims 8 and 16 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Vishin and Ricci (US 2004/0128547 A1, July 1, 2004). (Ans. 17–18.) Issues on Appeal Based on Appellants’ arguments, the issues on appeal are: I. Whether Vishin discloses an “interface” and “one interface of a plurality of interfaces,” as required by claim 1, and similar limitations of claims 9, 17, 23, 30, and 37 (App. Br. 8–18); Appeal 2012-009546 Application 12/146,657 4 II. Whether Vishin discloses “decoding the physical address using system-on-a-chip (SOC) memory map strappings,” as required by claim 17, and similar limitations of claims 3 and 10 (App. Br. 16– 18); III. Whether Vishin discloses “receiv[ing] the bit from a second TLB,” as required by claim 4 (App. Br. 19); and IV. Whether Vishin discloses a “multiplexer . . . configured to route the physical address,” as required by claim 7, and similar limitation of claim 15 (App. Br. 19–20). ANALYSIS I. Claim 1 The Examiner relies on Vishin as anticipating Appellants’ claim 1. (Ans. 3.) Specifically, the Examiner finds Vishin’s description of a node-ID representing clusters or nodes as “a bit indicating one interface of a plurality of interfaces,” as claim 1 requires. (Ans. 3.) Appellants dispute the Examiner’s findings. According to Appellants, “the ordinary and customary meaning of ‘interface’ is: a channel or bus with which communication necessitates an adaptation to particularities of that interface.” (App. Br. 10 (citing Spec. ¶ 3).) By contrast, Appellants argue, “Vishin describes nothing of this single coupling [between cluster 102 to network 114] operating as an interface.” (Id. at 12.) Because the clusters in Vishin are not interfaces, Vishin’s node-ID that indicates a cluster or node (i.e., an interface) cannot satisfy the “claim 1 storage of ‘a bit indicating one interface of a plurality of interfaces’ . . . .” (Id. at 9.) Similarly, Appellants argue Vishin does not disclose a “logic circuit configured to route a physical App App addr requ plura 102. below “Net inter “cha parti eal 2012-0 lication 12 ess . . . to o ires. (Id. a We are n lity of inte (Ans. 19. , each clu work Inter connection Althoug nnel or bu cularities o 09546 /146,657 ne of the t 15.) ot persuad rfaces in ) We agre ster 102 c connectiv between h Appellan s, with wh f that inte plurality o ed. The E order to m e. As sho ontains a “ ity (Switch the cluster Figure 9 d distributed ts argue a ich commu rface” (Ap 5 f interface xaminer f ake interco wn in figu communi , etc.) 114 s: epicts a pr address s n interface nication n p. Br. 10) s based on inds Vishi nnection re 9 of Vis cations int ” to provi ior art ystem. should be ecessitate , Appellan the bit,” a n’s figure of the seve hin, repro erface” co de the limited to s an adapt ts do not e s claim 1 9 shows a ral cluster duced nnected to a ation to th xplain s e Appeal 2012-009546 Application 12/146,657 6 why the channel between cluster 102 and network 114, which contains a “communication interface,” is not an “interface” even under such a construction. Instead, Appellants focus on the fact that each cluster shows a coupling to the network but “describes nothing of this single coupling operating as an interface.” (Id. at 12–13.) However, the claims do not require a specific interface. It is sufficient that Vishin explicitly describes each “coupling” to the network as a “communication interface.” Nor does the fact that each cluster contains only a “single coupling” or interface persuade us that the system, which comprises a plurality of clusters each having an interface (see Vishin, Fig. 9), does not include “a plurality of interfaces,” as the claims require. Similarly, even if the interface in each of the clusters are identical, as Appellants contend (App. Br. 13), the claims do not require different interfaces but only a “plurality of interfaces.” As the Examiner finds, the “node-ID 170 indicates the node [or cluster] of the system 100 at which the addressed data is stored.” (Ans. 19 (citing Vishin, col. 6, l. 67–col. 7, l. 1).) Thus, we agree Vishin’s “node-ID” discloses a “bit indicating one interface of a plurality of interfaces, the bit being associated with a physical address range,” as the claims require. Appellants argue the “logic circuit” required by claim 1 cannot be satisfied by Vishin because “Vishin cannot disclose a logic circuit configured to route a physical address associated with a bit that it does not have, to one of a plurality of interfaces when it shows no plurality of interfaces, based on the bit that it does not have.” (App. Br. 14.) However, as discussed supra, we are not persuaded the system in Vishin does not disclose each of these things. Accordingly, we are not persuaded of error in the Examiner’s finding that the required “logic circuit” is satisfied by the Appeal 2012-009546 Application 12/146,657 7 memory controller 112 and address bit merge circuit 167. (Ans. 3–4 (citing Vishin, col. 4, ll. 43–45, ll. 65–67 & Fig. 1 ).) Because we are not persuaded that Vishin does not disclose the limitations of claim 1, we sustain the Examiner’s rejection. With respect to independent claims 9, 23, 30, and 37, Appellants rely on their arguments for claim 1. (App. Br. 16–18.) Accordingly, for the foregoing reasons, we sustain the Examiner’s rejection of these claims as well. With respect to dependent claims 2, 5, 6, 8, 11–14, 16, 25–29, 32–36, and 39–43, which depend directly or indirectly from the foregoing independent claims, Appellants make no separate patentability arguments. Accordingly, we sustain the rejection of these claims as well. II. Claim 17 In rejecting independent claim 17, the Examiner relies on Vishin’s disclosure of cluster 102 consisting of processor 104, cache memory 120, and translation lookaside buffer 122 as disclosing “decoding the physical address using system-on-a-chip (SOC) memory map strappings,” as required the claim. (Ans. 20.) Appellants dispute the Examiner’s findings that cited portions of Vishin disclose “SOC memory map strappings.” (App. Br. 16–17.) On the record before us, we agree with Appellants. “A claim is anticipated only if each and every element as set forth in the claim is found, either expressly or inherently described, in a single prior art reference.” Verdegaal Bros., Inc. v. Union Oil Co. of Cal., 814 F.2d 628, 631 (Fed. Cir. 1987). Here, although the Examiner points to description of the cluster 120 in Vishin as satisfying the claim, the Examiner does not explain how this Appeal 2012-009546 Application 12/146,657 8 description expressly or inherently satisfies the required “memory map strappings.” Accordingly, we do not sustain the Examiner’s rejection of claim 17. With respect to dependent claims 18–22, which depend directly or indirectly from claim 17, we do not sustain the Examiner’s rejection for the same reasons. With respect to dependent claims 3 and 10, Appellants rely on their arguments for claim 17, namely that Vishin does not disclose the required “memory map strappings.” (App. Br. 18.) We generally agree that claims 3 and 10 have limitations similar to claim 17 requiring memory map strappings. Accordingly, we do not sustain the Examiner’s rejection of claims 3 and 10, for the same reasons. III. Claim 4 In rejecting claim 4, the Examiner relies on Vishin’s disclosure of “primary translation lookaside buffer (TLB)” and “remote translation lookaside buffer (RTLB)” as disclosing the “TLB” and “second TLB,” as required by the claim. (Ans. 5.) Appellants dispute the Examiner’s finding. Appellants point out the claim requires that the “storage module is configured to receive the bit from a second TLB.” (App. Br. 18.) However, the required “bit” is the bit from claim 1 that the Examiner finds is satisfied by the node-ID. (Ans. 3, 19.) Appellants contend there is no disclosure of the RTLB 160 receiving the node-ID. (App. Br. 18.) We agree. Although the node-ID is stored in the RTLB, (Vishin, col. 6, ll. 61–67), we cannot find evidence of record that the node-ID is received Appeal 2012-009546 Application 12/146,657 9 by or from the RTLB. Accordingly, we do not sustain the rejection of claim 4. IV. Claim 7 In rejecting claim 7, the Examiner relies on Vishin’s disclosure of “RTLB’s selection circuitry” as disclosing “a multiplexer . . . configured to route the physical address based on the selector and the bit,” as required by the claim. (Ans. 6.) Appellants dispute the Examiner’s finding. According to Appellants, Vishin’s selection circuitry is not capable of routing a physical address to “any ‘interface.’” (App. Br. 19–20.) We are not persuaded. The cited portion of Vishin describes the selection circuitry that “includes circuitry for selecting a single remote page table entry in accordance with predefined RPTE selection criteria . . . .” (Vishin, col. 3, l. 67–col. 4, l. 4.) As discussed supra, the remote physical page entry contains a node-ID that “indicates the node of the system 100 at which the addressed data is stored . . . .” (Vishin, col. 6, l. 63–col. 7, l. 1.) Based on these disclosures, we agree with the Examiner’s finding that Vishin discloses “a multiplexer . . . configured to route the physical address,” as the required by the claim. Accordingly, we sustain the rejection of claim 7. With respect to claim 15, Appellants make the same argument. (App. Br. 19–20.) Accordingly, we sustain the rejection of claim 15 for the foregoing reason. Appeal 2012-009546 Application 12/146,657 10 DECISION We affirm the Examiner’s final rejection of claims 1, 2, 5–9, 11–16, 23, 25–30, 32–37, and 39–43 under 35 U.S.C. § 103(a). However, we reverse the Examiner’s final rejection of claims 3, 4, 10, and 17–22 under 35 U.S.C. § 103(a). No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a) (1) (iv). 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