Ex Parte Imura

Patent Trial and Appeal Board

Feb 24, 2016

12705796 (P.T.A.B. Feb. 24, 2016)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/705,796 02/15/2010 Takashi Imura 11106/286 9345
85023 7590 02/25/2016
BGL/Seiko Instruments Inc.
P.O. Box 10395
Chicago, IL 60611
EXAMINER
GRUBB, MATTHEW
ART UNIT PAPER NUMBER
2838
MAIL DATE DELIVERY MODE
02/25/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte TAKASHI IMURA1
____________

Appeal 2014-004881
Application 12/705,796
Technology Center 2800
____________

Before BRADLEY R. GARRIS, BEVERLY A. FRANKLIN, and
CHRISTOPHER C. KENNEDY, Administrative Patent Judges.

KENNEDY, Administrative Patent Judge.

DECISION ON APPEAL

This is an appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1 and 2. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.

BACKGROUND
The subject matter on appeal relates to a voltage regulator having low
current consumption. Spec. ¶ 8; Claim 1. Claim 1 is reproduced below
from page 14 (Claims Appendix) of the Appeal Brief:

1 According to the Appellant, the real party in interest is Seiko Instruments
Incorporated. App. Br. 1.
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1. A voltage regulator, comprising:
an error amplifier for making a comparison between a voltage
based on an output voltage of the voltage regulator and a
reference voltage and outputting a voltage obtained by
amplifying a difference therebetween;
an output transistor for outputting the output voltage of the
voltage regulator based on the voltage output from the error
amplifier and a power supply voltage;
an overcurrent protection circuit including a first sense transistor
for sensing an output current from the output transistor, for
controlling the output transistor to lower the output voltage of the
voltage regulator when an overcurrent from the output transistor
is detected by the first sense transistor; and
a voltage control circuit which operates so that a drain voltage of
the output transistor is equal to a drain voltage of the first sense
transistor,
wherein the voltage control circuit includes a current circuit
comprising a current source connected to a current mirror circuit
and a second sense transistor for sensing the output current from
the output transistor, where the current mirror circuit supplies an
activation current for activating the voltage control circuit, and
the activation current supplied by the current mirror circuit is
limited based on the output current from the output transistor.

ANALYSIS
Claims 1 and 2 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Imura (US 2008/0265852 A1, published Oct. 30, 2008) in
view of Wrathall (US 2004/0021518 A1, published Feb. 5, 2004).
After review of the evidence in the appeal record and the opposing
positions of the Appellant and the Examiner, we determine that the
Appellant has not identified reversible error in the Examiner’s rejection.
Accordingly, we affirm the rejection for reasons set forth by the Examiner in
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the Final Action dated July 11, 2013, and the Answer. See generally Final
Act. 3–6; Ans. 2–10. We add the following for emphasis and completeness.
Relying primarily on Figure 2 of Imura, the Examiner finds that Imura
teaches each element of claim 1 except that it “is silent on whether the
current mirror circuit supplies the activation current.” Final Act. 5. The
Examiner explains two alternative interpretations of Figure 2:
In one interpretation, the Examiner interprets the current mirror
as the current mirror including at least references 5, 21, and 1,
however, a different interpretation would include a current
mirror which is connected to the current source such as a current
mirror within Reference 20 which would be connected to
Reference 121, would supply the activation current, and would
fulfill the limitations of the claim. Imura teaches that the current
circuit comprises (at least portions of) a generic operational error
amplifier 20. Construction of operational error amplifiers, such
as the Reference 20, were old and known at the time of invention
to include current mirror circuits to input a current and output an
appropriately scaled activation current for the core of the error
amplifier, as evidenced by Wrathall in 2004/0021518 (Wrathall).
Wrathall teaches a specific topology for an error amplifier, such
as the error amplifier 20 of Imura, including a current mirror (see
e.g., Wrathall — Figure 19, Reference MP5d, MP4d) wherein
the current mirror circuit inputs the current from a current source
(such as the current source 121 of Imura via Reference Vdd/Vss)
and outputs an activation current for activating the voltage
control circuit (e.g., the core of the error amplifier).
Id. at 5–6. The Examiner concludes that it would have been obvious to
include a current mirror circuit in item 20 of Imura Fig. 2 “to receive the
current from [items] 21 and 121 and output the activation current for the
error amplifier core in order to appropriate scale the current . . . which was
old and known at the time of the invention.” Id. at 6.
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The Appellant advances several arguments in opposition to the
Examiner’s rejection, which we address below:
1. The Examiner finds that operating current supply transistor 21, see
Imura Fig. 2, is equivalent to or otherwise renders obvious the claimed
“second sense transistor.” E.g., Ans. 3–5. The Appellant argues that the
“operating current supply transistor (21) differs from the recited second
sense transistor. Rather than limiting the operating current, the claimed
sense transistor senses the output of the output transistor, as recited by claim
1.” App. Br. 6. In the Reply Brief, the Appellant argues that “it is not
apparent that a basic current mirror is formed [by elements 1 and 21 of
Imura Fig. 2].” Reply Br. 3.
We are not persuaded by those arguments. As the Examiner explains
in the Answer, “the current output by 21 is based upon the output current
from the output transistor 1.” Ans. 5. That finding is supported by Imura,
which teaches that “[s]ince the gate of the operating current supply transistor
21 is connected to the gate of the output transistor 1, the operating current of
the error amplifier circuit 20 is in proportion to the current that flows in the
load from the output transistor 1.” Imura ¶ 37. The Appellant’s
unembellished arguments do not persuade us that the operating current
supply transistor 21 and the second sense transistor do not serve equivalent
functions, or that a person of ordinary skill in the art would not otherwise
have considered the claimed sense transistor to be obvious in light of the
operating current supply transistor 21 of Imura.
To the extent that the Appellant raises other differences between
Imura Fig. 2 and claim 1, e.g., App. Br. 6 (“The claimed current circuit
differs from the upper limiter circuit . . . disclosed by Imur[a].”), we are
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likewise not persuaded of reversible error. Merely alleging that differences
exist between the prior art and the claim, without explaining why those
differences result in nonobvious subject matter, is not sufficient to overcome
the case of obviousness set forth by the Examiner. Cf. In re Jung, 637 F.3d
1356, 1365 (Fed. Cir. 2011) (even if the examiner failed to make a prima
facie case, the Board would not have erred in framing the issue as one of
reversible error because “it has long been the Board’s practice to require an
applicant to identify the alleged error in the examiner’s rejections”).
2. The Appellant argues that “transistors MP4d and MP5d [of
Wrathall Fig. 19] are not connected to a current source and do not supply an
activation current.” App. Br. 6. That argument is not persuasive because it
does not address the Examiner’s rationale, i.e., substitution of the error
amplifier 1900 of Wrathall Fig. 19 for the error amplifier 20 of Imura Fig. 2.
Final Act. 5–6; Ans. 3. The Examiner finds that, when Wrathall’s current
mirror including transistors MP4d and MP5d are added to Figure 2 of Imura,
“the transistors are connected to a current source (e.g., Reference 21 and 121
are both sources of current, or ‘current sources’) and supply an activation
current . . . .” Ans. 3. The Appellant’s argument provides no basis to reject
those findings. See In re Keller, 642 F.2d 413, 426 (CCPA 1981) (“[O]ne
cannot show non-obviousness by attacking references individually where, as
here, the rejections are based on combinations of references.”).
3. Referring to claim 2, the Appellant argues that “there is no
suggestion by Imura of controlling the activation current by operation of the
current upper limiter circuit (121) and the cascade circuit (112).” App. Br.
7. We are not persuaded by that argument because it fails to rebut the
Examiner’s rationale persuasively. The Examiner finds that “activation
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current is limited by the second sense transistor [21] based on the output
current from the output transistor [1] . . . .” Final Act. 6. Imura supports
that finding. Imura ¶ 37. The Appellant’s argument provides no basis to
reject it. See Jung, 637 F.3d at 1365.
4. The Appellant argues that the Examiner “rel[ies] on the same
structural element disclosed by Imura as being responsive to two different
elements in claim 1.” App. Br. 8. That argument is not persuasive because
it fails to address the Examiner’s reliance on Wrathall as supplying the
current mirror circuit. See Final Act. 5–6; see also Keller, 642 F.2d at 426.
Under that rationale, the Examiner is not relying on the same structural
element of Imura as being responsive to two different elements. See Final
Act 5–6; Ans. 7. Moreover, even if the Examiner were relying on a single
element of Imura as serving two different functions, the Appellant fails to
persuasively explain why that would constitute reversible error in the
context of the obviousness rejection set forth by the Examiner.
5. The Appellant argues that the Examiner’s rejection is improperly
motivated by hindsight. App. Br. 10. However, the Appellant’s argument
addresses findings that the Examiner did not make. See id. The Examiner
does not propose replacement of elements 121 and 112 of Imura Fig. 2, as
suggested by the Appellant. See id. The Examiner proposes the substitution
of the error amplifier 1900 of Wrathall, see Wrathall Fig. 19, which includes
a current mirror, for the error amplifier 20 of Imura. See Final Act. 5–6.
Substitutions of one known element for another typically do not result in
nonobvious subject matter. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398,
416 (2007). The Appellant’s argument fails to persuasively explain why the
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substitution of the known error amplifier of Wrathall for the error amplifier
of Imura would not have been obvious to a person of ordinary skill in the art.
6. The Appellant argues that Imura teaches away from the use of a
current mirror. App. Br. 12 (citing Imura ¶ 12). Paragraph 12 of Imura
discusses a prior art embodiment depicted in Imura Fig. 5, see Imura ¶ 6,
and states that “the circuit using the above current mirror circuit has a
drawback that a current consumption increases . . . .”
We are not persuaded that ¶ 12 of Imura teaches away from the use of
a current mirror so as to render the proposed combination nonobvious. For a
reference to “teach away,” it must criticize, discredit, or otherwise
discourage the claimed solution. See In re Fulton, 391 F.3d 1195, 1201
(Fed. Cir. 2004). The existence of “better alternatives . . . does not mean
that an inferior combination is inapt for obviousness purposes.” In re
Mouttet, 686 F.3d 1322, 1334 (Fed. Cir. 2012). Moreover, to the extent that
increased current consumption is undesirable because it increases costs, that
consideration does not persuasively support a “teach away” argument. See
In re Farrenkopf, 713 F.2d 714, 718 (Fed. Cir. 1983) (“That a given
combination would not be made by businessmen for economic reasons does
not mean that persons skilled in the art would not make the combination
because of some technological incompatibility. Only the latter fact would be
relevant.”); see also Winner Int’l Royalty Corp. v. Wang, 202 F.3d 1340,
1349 n.8 (Fed. Cir. 2000) (“The fact that the motivating benefit comes at the
expense of another benefit . . . should not nullify its use as a basis to modify
the disclosure of one reference with the teachings of another. Instead, the
benefits, both lost and gained, should be weighed against one another.”).
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Additionally, that a prior art embodiment disclosed by Imura may
include a current mirror that increases current consumption does not
establish that the voltage regulator of Imura as modified by Wrathall,
proposed by the Examiner, would possess the same “drawback.” The
Appellant does not address the Examiner’s rationale in the Appeal Brief but
argues for the first time in the Reply Brief that “[e]ven if one skilled in the
art were to . . . insert[] the identified transistors [from] Wrathal[l] in the error
amplifier circuit (20) [of Imura], the result is [increased current
consumption].” Reply Br. 5. We will not consider new arguments raised in
the Reply Brief because the Appellant has not shown good cause for failing
to present those arguments in the opening Appeal Brief. See 37 C.F.R.
§ 41.41(b)(2). Even if we were to consider that argument, however, the
Appellant provides no evidence or persuasive technical reasoning to support
the assertion that Imura as modified by Wrathall would have undesirable
current consumption.
7. In the Reply Brief, the Appellant characterizes the Examiner’s
proposal of substituting the error amplifier 1900 of Wrathall for the error
amplifier 20 of Imura as a “changed basis for the rejection.” Reply Br. 4–6.
As explained above, however, the Examiner clearly presented that basis for
rejection in the Final Action, see Final Act. 5–6, and the Appellant did not
meaningfully address it in the opening Appeal Brief. To the extent that the
Reply Brief raises new arguments, we decline to consider them. See 37
C.F.R. § 41.41(b)(2).
* * *
For those reasons, the Appellant has failed to identify reversible error
in the Examiner’s rejection. We therefore affirm the rejection.
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CONCLUSION
We AFFIRM the Examiner’s rejection of claims 1 and 2.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).

AFFIRMED