10611272 (B.P.A.I. Sep. 16, 2009)

Ex Parte Hurley

Board of Patent Appeals and InterferencesSep 16, 2009

10611272 (B.P.A.I. Sep. 16, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________________ Ex parte WILLIAM M. HURLEY ____________________ Appeal 2008- 004593 Application 10/611,272 Technology Center 2100 ____________________ Decided: September 16, 2009 ____________________ Before HOWARD B. BLANKENSHIP, ST. JOHN COURTENAY III, and DEBRA K. STEPHENS, Administrative Patent Judges. STEPHENS, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Appellant appeals under 35 U.S.C. § 134(a) from a final rejection of claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. Appeal 2008-004593 Application 10/611,272 2 Introduction According to Appellant, the invention is a circuit and method for providing a power-on self test capability for peripheral devices that allows direct testing of address-line data (Abstract). A multiplexer circuit allows the read address line outputs of a microprocessor to be directly returned to the data inputs of the microprocessor to provide direct verification of the integrity of the read-address connection (id.).1 Exemplary Claim(s) Claim 1 is an exemplary claim and is reproduced below: An electronic device comprising: a microprocessor; an embedded device, the embedded device having at least one addressable register connected to be addressed by, written to, and read from by the microprocessor; and a multiplexer circuit having selectable first and second modes of operation, wherein when the multiplexer is in the first mode of operation, then an address bus output of the microprocessor is connected to a data bus input of the microprocessor, and wherein when the multiplexer is in the second mode of operation, then an output of the addressable register is connected to the data bus input of the microprocessor. 1 We note Appellant inadvertently filed Drawings in the Reply Brief filed January 14, 2008 that belong to another case. We find this to be harmless error as Appellant had previously filed the correct Drawings with the Appeal Brief filed July 31, 2007. Thus, we will not consider those Drawings filed with the Reply Brief. Appeal 2008-004593 Application 10/611,272 3 Prior Art The prior art relied upon by the Examiner in rejecting the claims on appeal is: Keeley 4,575,792 Mar. 11, 1986 Auvinen 5,276,833 Jan. 4, 1994 Culley 6,000,040 Dec. 7, 1999 Rejections The Examiner rejected claims 1-5, 7-12, 14-18, and 20 under 35 U.S.C. § 103(a) as being unpatentable over Auvinen and Keeley. The Examiner rejected claims 6, 13, and 19 under 35 U.S.C. § 103(a) as being unpatentable over Auvinen, Keeley, and Culley. ISSUE 35 U.S.C. § 103(a): claims 1-5, 7-12, 14-18, and 20 Appellant asserts his invention is not obvious over Auvinen and Keeley (App. Br. 17-18). Specifically, Appellant argues Keeley does not teach an address bus output of the microprocessor is connected to a data bus input of the microprocessor in a first mode of operation of the multiplexer circuit (App. Br. 22-23). The Examiner finds Keeley teaches a CPU 10 and a cache unit 20 are interconnected through the address, control, and data lines of a private interface 18 through the CPU/test interface (Ans. 11). Issue: Has Appellant met the burden of showing the Examiner erred in finding Keeley teaches or suggests that a multiplexer circuit in a first mode of operation connects an address bus of a microprocessor to a data bus input of the microprocessor? Appeal 2008-004593 Application 10/611,272 4 FINDINGS OF FACT (FF) Keeley Reference (1) Keeley teaches test mode logic circuits in a cache memory section of a cache unit enable cache memories to be tested without controller interference while using the controller interface circuits (Abstract). (2) The registers of block 20-52 are connected to receive address signals BAR03000010 through BAR220010 from the address interface lines which comprise interface connector 20-24a (col. 11, ll. 12-15). A CPU Test Interface 20-22 is connected to a Test Interface 22 which includes data and address registers 22-10, 22-18 (col. 13, ll. 60-col. 14, ll. 19 and Fig. 2). (3) The CPU 10 performs the series of set-ups 30-16 and 30-22 (col. 18, ll. 26-27). The cache memory 20-4 and directory 20-8 are placed in a test mode wherein such testing can be carried out without interference from cache controller 20-2 (col. 18, ll. 29-33). (4) A last step or operation performed by CPU 10 is initiating signals for carrying out operations on cache buffer memory 20-4 and directory memory 20-8 (col. 18, ll. 33-35). The CPU 10 performs the testing using interface 22 in the same manner as the automatic test equipment 24 (col. 18, ll. 36-38). PRINCIPLES OF LAW In rejecting claims under 35 U.S.C. § 103, it is incumbent upon the Examiner to establish a factual basis to support the legal conclusion of obviousness. See In re Fine, 837 F.2d 1071, 1073, 5 USPQ2d 1596, 1598 (Fed. Cir. 1988). In so doing, the Examiner must make the factual determinations set forth in Graham v. John Deere Co., 383 U.S. at 17, 148 USPQ at 467 (1966). In addition to the findings under Graham, there must Appeal 2008-004593 Application 10/611,272 5 also be “some articulated reasoning with some rational underpinning to support the legal conclusion of obviousness.” See In re Kahn, 441 F.3d 977, 988, 78 USPQ2d 1329, 1336 (Fed. Cir. 2006) (cited with approval in KSR Int’l v. Teleflex, Inc., 550 U.S. 398, 418 (2007)). ANALYSIS We find, as argued by Appellant (App. Br. 22-23 and Reply 15), that the Examiner has not been clear in identifying where Keeley teaches or suggests when the multiplexer is in the first mode of operation, then an address bus output of the microprocessor is connected to a data bus input of the microprocessor as recited in claim 1. (See also analogous language in claims 8 and 14.) We find Keeley teaches an address bus and modes of operation (FF 2 and FF 3); however, the Examiner has not specifically shown where Keeley teaches or suggests the address bus output of the microprocessor is connected to a data bus input of the microprocessor. Therefore, it would require speculation on our part to find Keeley teaches or suggests this limitation. CONCLUSION Based on the findings of facts and analysis above, we conclude Appellant has met the burden of showing the Examiner erred in finding Keeley teaches or suggests a multiplexer circuit in a first mode of operation connects an address bus of a microprocessor to a data bus input of the microprocessor. Accordingly, we conclude Appellant has met the burden of showing the Examiner erred in rejecting claims 1, 8, and 14 under 35 U.S.C. § 103(a) for obviousness over Auvinen and Keeley. Since claims 2-5 and 7 depend from independent claim 1, claims 9-12 depend from independent Appeal 2008-004593 Application 10/611,272 6 claim 8, and claims 15-18 and 20 depend from independent claim 14, we conclude Appellant has met the burden of showing the Examiner erred in rejecting claims 2-5, 7, 9-12, 15-18, and 20 under 35 U.S.C. § 103(a) for obviousness over Auvinen and Keeley. Additionally, since claim 6 depends from independent claim 1, claim 13 depends from independent claim 8, and claim 19 depends from independent claim 14, we conclude Appellant has met the burden of showing the Examiner erred in rejecting claims 6, 13, and 19 under 35 U.S.C. § 103(a) for obviousness over Auvinen, Keeley, and Culley. DECISION The Examiner’s rejection of claims 1-5, 7-12, 14-18, and 20 under 35 U.S.C. § 103(a) as being obvious over Auvinen and Keeley is reversed. The Examiner’s rejection of claims 6, 13, and 19 under 35 U.S.C. § 103(a) as being obvious over Auvinen, Keeley, and Culley is reversed. REVERSED Erc DOCKET CLERK P.O. DRAWER 800889 DALLAS, TX 75380