Ex Parte Huppenthal

Board of Patent Appeals and Interferences

May 10, 2011

10340400 (B.P.A.I. May. 10, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte JON M. HUPPENTHAL
____________

Appeal 2009-010115
Application 10/340,400
Technology Center 2100
____________

Before ROBERT E. NAPPI, JOHN A. JEFFERY, and DENISE M.
POTHIER, Administrative Patent Judges.

POTHIER, Administrative Patent Judge.

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1, 3-7, 9-21, and 23-27. Claims 2, 8, and 22 have been
canceled. Br. 2. We have jurisdiction under 35 U.S.C. § 6(b). We affirm.

STATEMENT OF THE CASE
Appellant’s invention relates to adaptive processors in a clustered
computing system. See generally Spec. 3-4. Claim 1 is reproduced below
with the key disputed limitations emphasized:
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1. A clustered computer system comprising:
at least first and second independent processing nodes;
a cluster interconnect external to and coupling said first and
second processing nodes
wherein at least said first processing node comprises a
reconfigurable processing element coupled to said cluster
interconnect through a peripheral interface and
wherein at least said second processing node comprises a non-
reconfigurable processing element coupled to said cluster interconnect
through a network interface card.

The Examiner relies on the following as evidence of unpatentability:
Muthujumaraswathy US 6,279,045 B1 Aug. 21, 2001
Bruckert US 2002/0049859 A1 Apr. 25, 2002

Helen Chen & Pete Wyckoff, Performance Evaluation of a Gigabit
Ethernet Switch and Myrinet Using Real Application Cores, 8th
Annual Sym. On High-Performance Interconnects 1-81 (2000)
(“Chen”).

THE REJECTIONS
1. The Examiner rejected claims 1, 3, 4, 7, 9-18, 21, and 23-27
under 35 U.S.C. § 103(a) as unpatentable over Bruckert and
Muthujumaraswathy. Ans. 3-16.2
2. The Examiner rejected claims 5, 6, 19, and 20 under 35 U.S.C.
§ 103(a) as unpatentable over Bruckert, Muthujumaraswathy, and Chen.
Ans. 8-9.

1 Eight printed pages of this reference were provided, and these page
numbers correspond sequentially to the pages provided.
2 Throughout this opinion, we refer to the Appeal Brief filed March 13, 2007
and the Examiner’s Answer mailed June 26, 2007.
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THE OBVIOUSNESS REJECTION OVER BRUCKERT
AND MUTHUJUMARASWATHY

Regarding representative independent claim 1, the Examiner finds that
Bruckert discloses all recited limitations, except for both a reconfigurable
and non-reconfigurable processing element. Ans. 3-4, 9-12. The Examiner
relies on Muthujumaraswathy to teach the missing features. Ans. 4, 12-13.
Appellant admits that Muthujumaraswathy teaches non-configurable
and reconfigurable processors but that the processors are on a single chip.
Br. 6. For this reason, Appellant asserts that the Muthujumaraswathy fails to
discuss a clustered computer environment where an interconnect is external
to independent non-configurable and reconfigurable processors (Br. 6, 10)
and the Examiner has not provided a motivation to combine
Muthujumaraswathy with Bruckert to produce the processors coupled as
recited (Br. 7-9).
The issues before us, then, are as follows:

ISSUES
(1) Under § 103, has the Examiner erred in rejecting claim 1 by
finding that Bruckert and Muthujumaraswathy collectively would have
taught or suggested a cluster interconnect external to and coupling the first
processing node comprising a reconfigurable processing element and a
second processing node comprising a non-reconfigurable processing
element?
(2) Has the Examiner articulated a reason to combine the cited
references with some rational underpinning to justify the Examiner’s
obviousness conclusion?
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FINDINGS OF FACT (FF)
1. We adopt the Examiner findings as our own. Ans. 3-4, 9-13, 17-
23.
2. Bruckert discloses processors (e.g., CPUs 102, 110, 410) or
resources containing CPUs (e.g., 302) connected to each other through a
fabric or switch (e.g., 106, 114, 304, 412). Bruckert, ¶¶ 0026-27, 0034-36;
Figs. 1a-3.
3. Muthujumaraswathy teaches an integrated circuit (IC) chip 100
having reconfigurable logic 102 and a media processor 104.
Muthujumaraswathy, col. 1, l. 66 – col. 2, l. 15; Fig. 1.
4. Muthujumaraswathy’s overall system 300 includes an electronic
component 302 having Muthujumaraswathy’s inventive techniques and
another electronic component 304 on an interconnection substrate 306, as
well as other peripheral devices (e.g., 310, 312, 314), including a printer and
video monitor. Muthujumaraswathy, col. 8, ll. 27-44; Fig. 3.

ANALYSIS
Based on the record before us, we find no error in the Examiner’s
obviousness rejection of representative claim 1 which calls for, in pertinent
part, a cluster interconnect external to and coupling a first independent
processing node having a non-configurable processing element and a second
independent processing node having a reconfigurable processing element.
Appellant asserts that Muthujumaraswathy fails to discuss the claimed
cluster interconnect external to independent non-configurable and
reconfigurable processors. Br. 6, 10. As the Examiner explains (see Ans. 3-
4, 9-10, 17) and as we adopt (see FF 1), Bruckert – not Muthujumaraswathy
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– teaches first and second independent processing nodes (e.g., 102 or 302)
and an external cluster interconnect (e.g., fabrics shown in Figs. 1a-3). See
FF 2. Muthujumaraswathy has been cited to teach the details of these
processing nodes. See FF 1 (citing to Ans. 4, 11-13, 17). Thus, attacking
Muthujumaraswathy individually does not show nonobviousness because the
rejection is based on Bruckert and Muthujumaraswathy collectively. See In
re Merck & Co., Inc., 800 F.2d 1091, 1097 (Fed. Cir. 1986).
Additionally, we agree with the Examiner that claim 1 does not
require that the cluster interconnect to be external to an integrated chip (IC),
but rather external to first and second processing nodes. See Ans. 18.
However, Appellant notes that claim 1 also recites the reconfigurable
processing element is coupled to the cluster interconnect through a
peripheral interface and the non-configurable element is coupled to the
cluster interconnect through a network interface card (NIC). See Br. 11.
Specifically, Appellant states that motherboards of a single IC do not
possess such claimed interfaces. See id. Even assuming, without deciding,
that Appellant is correct, we are still not persuaded that the cited references
collectively fail to teach the disputed external interconnect limitation.
The Examiner cites to Muthujumaraswathy to provide the inner
details for two of Bruckert’s processors. See Ans. 4, 17-18. To elaborate,
the Examiner is not proposing a wholesale replacement of all of Bruckert’s
processing nodes (e.g., CPUs 102, 302, 410) (see FF 2) with a single
Muthujumaraswathy’s processing element. See Ans. 4, 17-18. Rather, two
of Bruckert’s processors are each being substituted with a processor taught
by Muthujumaraswathy. See id. Thus, when replacing each of these
Bruckert’s processors (e.g., 302 in Fig. 2 (see FF 2)) with a
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Muthujumaraswathy’s processor (e.g., IC chip 100), the combination
predictably yields or results in no more than two independent processing
nodes both having a reconfigurable processing element (e.g., 102) and a
non-configurable processing element (e.g., 104) (see FF 3). See KSR Co.
Int’l v. Teleflex Inc., 550 U.S. 398, 417 (2007). Such a combination would
predictably result in the cluster interconnect (e.g., Bruckert’s fabric 304)
being external to and coupling a first processing node (e.g., one of
Bruckert’s substituted CPUs in resource 302) having a reconfigurable
processing element (e.g., Muthujumaraswathy’s 102) and a second
processing node (e.g., the second of Bruckert’s substituted CPUs in another
resource 302) having a non-reconfigurable processing element (e.g.,
Muthujumaraswathy’s 104). See id; see also Ans. 21.
Also, claim 1 uses an open-ended transitional phrase, “comprising,”
which does not exclude additional, unrecited elements. See Mars, Inc. v.
H.J. Heinz Co., 377 F.3d 1369, 1376 (Fed. Cir. 2004). Thus, the resulting
Bruckert/Muthujumaraswathy system can have a first processing node with a
reconfigurable processing element (as well as a non-reconfigurable
processor) and a second processing node with a non-reconfigurable
processing element (as well as a reconfigurable processor) and still teach all
the recited limitations in claim 1. Additionally, only one of Bruckert’s
processing nodes needs to be substituted with Muthujumaraswathy’s
processor 100 having a reconfigurable processor to teach the disputed
limitations in claim 1. The Examiner further refers to Muthujumaraswathy’s
teaching (see Ans. 4) demonstrating a reconfigurable processor (e.g., 308)
externally interconnected to other devices (e.g., printer) that have a
non-reconfigurable processor (see FF 4).
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Regarding Appellant’s assertions that the Examiner failed to present a
motivation to combine the references and relies on impermissible hindsight
(Br. 7-9), we again adopt the Examiner’s findings discussing
Muthujumaraswathy and its teaching to improve Bruckert’s speed, density,
and power. See FF 1 (citing to Ans. 4, 19, 21-22). Based on
Muthujumaraswathy’s teachings, an ordinarily skilled artisan would have
recognized that Muthujumaraswathy’s technique used to improve processing
speed, density, and power can be equally be applied to Bruckert’s processors
to improve Bruckert’s system in the same manner. See KSR, 550 U.S. at
417. The Examiner has therefore articulated a reason with some rational
underpinning to justify the obviousness conclusion. See id. at 418.
Lastly, we find the claimed invention is within a predictable art, and,
as discussed above, combining Muthujumaraswathy with Bruckert would
have predictably yielded the recited processing nodes externally coupled to
the cluster interconnect. Because such a combination does not render
Bruckert’s device inoperable and Appellant has provided no evidence to the
contrary (Br. 9-10), we find the Examiner has provided a sufficient basis for
a reasonable expectation of success.
As to any remaining arguments, we adopt the Examiner’s findings.
See FF 1.
For the foregoing reasons, Appellant has not persuaded us of error in
the obviousness rejection of: independent claim 1 and claims 3, 4, 7, 9-18,
21, and 23-27 not separately argued with particularity (Br. 5-11).

Appeal 2009-010115
Application 10/340,400

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THE OBVIOUSNESS REJECTION OVER BRUCKERT,
MUTHUJUMARASWATHY, AND CHEN

Claims 5, 6, 19, and 20 are rejected under 35 U.S.C. § 103 over
Bruckert, Muthujumaraswathy, and Chen. Ans. 8-9. Appellant does not
separately argue these claims or this rejection. See Br. 4-11. For the reasons
stated above in connection with claim 1 and claim 14, which is not
separately argued, Appellant has not persuaded us of error. We therefore
will sustain the § 103 rejection for claims 5, 6, 19, and 20.

CONCLUSION
The Examiner did not err in rejecting claims 1, 3-7, 9-21, and 23-27
under § 103.

DECISION
The Examiner’s decision rejecting claims 1, 3-7, 9-21, and 23-27 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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