Ex Parte HUNG et al

Patent Trial and Appeal Board

Mar 30, 2017

13548924 (P.T.A.B. Mar. 30, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/548,924 07/13/2012 Ching-Yu HUNG TI-70051 5262
23494 7590 04/03/2017
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS, TX 75265
EXAMINER
PETRANEK, JACOB ANDREW
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
04/03/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
uspto@ti.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte CHING-YU HUNG, SHINRIINAMORI,
JAGADEESH SANKARAN, and PETER CHANG
Appeal 2017-001378
Application 13/548,924
Technology Center 2100
Before KRISTEN L. DROESCH, JUSTIN BUSCH, and
LINZY T. McCARTNEY, Administrative Patent Judges.
McCARTNEY, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a rejection of claims
1, 2, 4, 6, 13, 14, and 23—25. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
Appeal 2017-001378
Application 13/548,924
STATEMENT OF THE CASE
Claim 1 illustrates the claimed subject matter:
1. A processor, comprising:
a scalar processor core; and
a vector coprocessor core coupled to the scalar processor
core;
the scalar processor core comprising:
a program memory interface through which the
scalar processor retrieves instructions from a program
memory, the instructions comprising scalar instructions
executable by the scalar processor and vector instructions
executable by the vector coprocessor core;
a coprocessor interface through which the scalar
processor passes the vector instructions to the vector
coprocessor;
the vector coprocessor core, comprising:
a plurality of execution units; and
a vector command buffer including:
a predecode first-in-first-out buffer having an
input receiving vector instructions from said scalar
processor and an output,
a vector instruction decoder having an input
connected to said output of said predecode first-in-
first-out buffer and an output, said vector instruction
decoder decoding a vector instruction received from
said predecode first-in-first-out buffer and
supplying a decoded vector instruction at said
output,
a first decoded vector command storage
buffer having an input connected to said output of
said vector instruction decoder and an output, for
storing a decoded vector instruction,
a second decoded vector command storage
buffer having an input connected to said output of
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Application 13/548,924
said vector instruction decoder and an output, for
storing a decoded vector instruction, and
a multiplexer having a first input connected
to said output of said first decoded vector command
storage buffer, a second input connected to said
output of said second decoded vector command
storage buffer and an output supplying a decoded
vector instruction to said plurality of execution
units, said multiplexer repetitively
supplying said decoded vector
instruction stored in a first one of said first
and second decoded vector command storage
buffers to said plurality of execution units via
said output until execution of said decoded
vector instruction is complete, and
thereupon supplying said decoded
vector instruction stored in a second one of
said first and second decoded vector
command storage buffers to said plurality of
execution units via said output enabling said
first one of said first and second decoded
vector command storage buffers to store a
further decoded vector instruction received
from said vector instruction decoder.
REJECTION
Claims 1, 2, 4, 6, 13, 14, and 23—25 stand rejected under 35 U.S.C.
§ 103(a) as unpatentable over Khan et al. (US 8,359,462 Bl; Jan. 22, 2013),
Singh et al. (US 2005/0102659 Al; May 12, 2005), Ganapathy et al. (US
6,598,155 Bl; July 22, 2003), and Official Notice.
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Appeal 2017-001378
Application 13/548,924
ANALYSIS
Appellants argue Ganapathy does not teach or suggest the first and
second “decoded vector command storage buffers” recited in claim 1. See
App. Br. 15—17. According to Appellants, Ganapathy discloses that registers
803A—803N store instructions prior to decoding, not decoded vector
instruction as required by claim 1. See id. Appellants assert the Examiner
found only Ganapathy teaches or suggests these limitations. See id. at 17—
19.
We find Appellants’ arguments unpersuasive. Contrary to
Appellants’ arguments, the Examiner did not find Ganapathy alone teaches
or suggests the disputed limitations. The Examiner explicitly found a
combination of Ganapathy, Singh, and Khan teaches or suggests the recited
first and second “vector command storage buffers” recited in claim 1. See
Final Act. 6 (citing Ganapathy Figure 8B, columns 15 and 16; Singh Figure
2; and Khan Figure 6 with respect to the recited first and second “vector
command storage buffers”); see id. (explaining “[t]he combination
implements the loop buffer of Ganapathy and Khan to implement storing
nested loops” and the entries storing outer and inner loop instructions
respectively correspond to the recited first and second buffers). Appellants’
arguments against Ganapathy alone have not persuaded us the Examiner
erred. “[0]ne cannot show non-obviousness by attacking references
individually where, as here, the rejections are based on combinations of
references.” In re Keller, 642 F.2d 413, 426 (CCPA 1981).
Appellants also contend Ganapathy does not teach or suggest “the
alternate selection of two buffers” as required by claim 1. See App. Br. lb-
17. Appellants argue the “alternate selection ... of the multiplexer” recited
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Application 13/548,924
in claim l“is not limited to loop instructions” and “Ganapathy . . . teaches
employing different numbers of registers . . . depending on loop length,
contrary to the recitation in” claim 1. Id. at 17.
As an initial matter, claim 1 does not recite “the alternate selection of
two buffers.” Claim 1 recites a multiplexer that “repetitively supplies] said
decoded vector instruction stored in a first one of said first and second
decoded vector command storage buffers . . . until execution of said decoded
vector instruction is complete.” App. Br. 21. “[Thereupon,” the
multiplexer “sup[lies] said decoded vector instruction stored in a second one
of said first and second decoded vector command storage buffers to said
plurality of execution units.” Id. These limitations differ in scope from the
simple “alternate selection of two buffers” argued by Appellants; therefore,
Appellants’ arguments are incommensurate with the scope of the claims.
Regardless, Ganapathy discloses “a first in first out (FIFO) type of
buffer” known as a “loop buffer” that “repeatedly output[s] each instruction
stored therein in a circular fashion in order to repeat executing the
instructions within the sequence of the loop.’ '' Ganapathy 13:60-61, 14: 29—
32 (emphases added); Figs. 7, 8A, 8B (depicting loop buffer block
diagrams). Ganapathy discloses a multiplexer “selects the output of one of
[instruction] registers [in the loop buffer] as its output and the instruction
that is to be executed on the next cycle.” Id. at 16:67—17:2. The Examiner
found these teachings, combined with the teachings of Singh and Khan,
would have taught or suggested the recited multiplexer to one of ordinary
skill in the art. See Final Act. 6—7.
Appellants’ arguments have not persuaded us the Examiner erred.
Although it may be true that claim 1 is not “limited to loop instructions” as
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argued by Appellants, see App. Br. 16, claim 1 also does not preclude loop
instructions. And Appellants have provided no persuasive evidence or
reasoning to support the assertion that employing differing number of
registers depending on loop length is “contrary to the recitation in” claim 1.
We see nothing in claim 1 that would preclude employing differing numbers
of registers depending on loop length.
Appellants also take issue with the Examiner’s conclusion that claim 1
does ‘“not require that the first one [of the vector command storage buffers]
is different from the second one’ [of the vector command storage buffers].”
See Reply Br. 2. Appellants argue this conclusion is contrary to the
language of claim 1 and “would result in the multiplexer supplying the
decoded vector instruction after ‘execution of said decoded vector
instruction is complete.’” See id. Finally, Appellants contend the cited
portions “make clear that the loop buffer registers ... are loaded based upon
the loop parameters and not the selection of the multiplexer” as required by
claim 1. Reply Br. 4.
We find Appellants’ arguments unpersuasive. Even assuming the
Examiner erroneously concluded that the first and second vector command
storage buffers can be the same buffer, the cited portions of Ganapathy
disclose a plurality of buffers that hold instructions, see Ganapathy Fig. 8B,
items 803A—803N. The Examiner also found Ganapathy, in combination
with Singh and Khan, teach or suggest supplying decoded nested vector loop
operations to a multiplexer. Ans. 5—6. The Examiner found “[t]he
outputting of a first next vector loop operation reads upon the first
‘supplying’ limitation and the outputting of a second nested vector loop
operation reads upon the ‘thereupon supplying’ limitation.” Id. at 5.
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Because Ganapathy teaches these loop operations reside in different loop
instruction registers, see Ganapathy Fig. 8B, items 803 A—803N; 14:15—32,
Ganapathy suggests multiple distinct buffers that hold different instructions.
As for Appellants’ contention that Ganapathy “make[s] clear that the
loop buffer registers ... are loaded based upon the loop parameters and not
by the selection of the multiplexer,” Reply Br. 4, Appellants waived this
contention by failing to raise it in their Appeal Brief. See 37 C.F.R. §§
41.37(c)(l)(iv), 41.41(b)(2); In reLovin, 652 F.3d 1349 (Fed. Cir. 2011). In
any event, claim 1 does not require loading memory locations based on
multiplexer selection.
For the above reasons, we sustain the Examiner’s rejection of claim 1.
Because Appellants have not presented separate, persuasive patentability
arguments for claim 2, 4, 6, 13, 14, and 23—25, we also sustain the
Examiner’s rejection of these claims.
DECISION
We affirm the Examiner’s rejection of claims 1, 2, 4, 6, 13, 14, and
23-25.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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