Ex Parte Hoayun

Patent Trials and Appeals Board

Mar 25, 2019

13960940 - (D) (P.T.A.B. Mar. 25, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/960,940 08/07/2013 PaulHoayun
123305 7590 03/27/2019
Procopio, Cory, Hargreaves & Savitch LLP/Qualcomm
525 B Street, Suite 2200
San Diego, CA 92101
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
l 16418-366UT1 3502
EXAMINER
WADDY JR, EDWARD
ART UNIT PAPER NUMBER
2135
NOTIFICATION DATE DELIVERY MODE
03/27/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing@procopio.com
ocpat_uspto@qualcomm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte PAUL HOA YUN 1
Appeal2018-002639
Application 13/960,940
Technology Center 2100
Before CARLA M. KRIVAK, HUNG H. BUI, and JON M. JURGOV AN,
Administrative Patent Judges.
KRIVAK, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner's
Final Rejection of claims 1-20, which are all the claims pending in the
application. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm-in-part.
1 Appellant identifies the real party in interest as Qualcomm Technologies
International, Ltd. (see App. Br. 2).
Appeal2018-002639
Application 13/960,940
STATEMENT OF THE CASE
Appellant's invention is directed to a method and system for patching
one time programmable (OTP) memory by modifying a data word of the
OTP memory to a data value that will cause a processor to read a patch code
for the OTP memory (Spec. 1: 1---6; Abstract).
Claims 1, 12, and 18 are independent. Claims 1 and 12, reproduced
below, are exemplary of the subject matter on appeal.
1. A method of configuring patch code for a one time
programmable memory, the one time programmable memory
comprising a plurality of data words, each data word of the
plurality of data words comprising a plurality of programmable
data bit cells, the method comprising:
identifying a first location in the one time programmable
memory where a patch is required;
modifying the data word of the plurality of data words at
the first location to a predetermined data value;
writing patch code for the patch at a patch code location;
and
storing the patch code location.
12. A method of operating a system comprising a
processor and a one time programmable memory, the method
compnsmg:
reading a data word at a first location in the one time
programmable memory;
determining if a value of the data word corresponds to an
exception instruction of the processor, the exception instruction
corresponding to the data value for all bits of the data word at
the first location being in a programmed state; and
if the value of the data word is determined to correspond
to the exception instruction of the processor:
performing a look up in a patch table for a patch
code location; and
reading data at the patch code location.
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Application 13/960,940
REJECTION and REFERENCES
The Examiner rejected claims 1-20 under 35 U.S.C. § 103 based upon
the teachings of Moyer (US 2002/0124161 Al, published Sept. 5, 2002) and
Kosaka (US 6,298,481 B 1, issued Oct. 2, 2001 ).
ANALYSIS
Claims 1, 2, 4, 10, 11, and 18
With respect to claim 1, Appellant contends neither Moyer nor
Kosaka teaches the claimed "one time programmable memory," which is a
"memory that can be programmed only once" (App. Br. 4). Rather, Moyer
only teaches "read only memory (ROM)," and "unlike OTP memory, ROM
cannot be modified at all." Similarly, Kosaka's memory is a "two time
programmable memory (i.e., reprogrammable memory)" (App. Br. 5 ( citing
Moyer ,r,r 2--4); Reply Br. 3, 5 (citing Kosaka col. 7, 11. 51-55)). Appellant
further contends "Moyer, either alone or in combination with Kosaka, fails
to disclose ... 'modifying the data word ... at the first location[, identified
in the one time programmable memory as requiring a patch,] to a
predetermined value"' (App. Br. 4). Particularly, Appellant argues
"embodiments of Claim 1 modify the value of the data word in the OTP
memory to identify to the processor when an address of that data word
requires a patch," in contrast to Moyer "which compare[s] the address of the
data word to reference addresses in order to identify addresses which require
patching" (App. Br. 6). We do not agree.
We agree with and adopt the Examiner's findings as our own.
Particularly, we agree with the Examiner a skilled artisan would understand
memory patching could be applied to Moyer's ROM, which is a one time
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Application 13/960,940
programmable memory (Final Act. 18-19, 28; Ans. 75-76). 2 Moyer teaches
"[p ]rogram memory 200 [to be patched] may reside in any memory within
data processing system 100, such as, for example, in ROM 106" or it "may
reside in an external ROM ... or in any other embedded or external
memory" (Final Act. 18-19 ( citing Moyer ,r 20, Fig. 2) ( emphasis omitted)).
Thus, a skilled artisan, viewing Moyer's teaching, would recognize Moyer's
ROM memory ( embedded or external), encompasses a one time
programmable memory, as claimed (Ans. 76, 79).
Appellant's arguments regarding the claimed "modifying the data
word" are also unpersuasive because they are not commensurate with the
scope of claim 1. Claim 1 does not require modifying the data word "to
signal or identify to the processor that the location requires a patch" or "to
identify to the processor when an address of that data word requires a patch"
2 For example, ROMs are known as one time programmable memories to
one skilled in the art of computer storage-see, e.g., Introduction to Digital
Electronics (John Crowe and Barrie Hayes-Gill, Newnes 1998), 240, § 10.1
("fuse programmed ROM devices are programmed by blowing small fuses
and hence are sometimes called One Time Programmable ROM or
OTPROM"); SD Card Projects Using the PIC Microcontroller (Dogan
Ibrahim, Elsevier Ltd. 2010), 5, § 1.2.4 ("Erasable Programmable Read Only
Memory ... Some versions of EPROMs, known as one time programmable
(OTP) EPROMs, can be programmed using a suitable programmer device,
but these memories cannot be erased"); https://en.wikipedia.org/wiki/Read-
only_memory (last accessed Feb. 27, 2019) ("Programmable read-only
memory (PROM), or one-time programmable ROM (OTP), can be written to
or programmed via a special device called a PROM programmer. Typically,
this device uses high voltages to permanently destroy or create internal links
(fuses or antifuses) within the chip.") (emphasis omitted); and
https://en.wikipedia.org/wiki/EPROM (last accessed Feb. 27, 2019) ("OTP
( one-time programmable) chips were introduced .... OTP versions of both
EPROMs and EPROM-based microcontrollers are manufactured.").
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Application 13/960,940
as Appellant argues (App. Br. 6-7). Appellant's Specification also does not
restrict "modifying a data word" to identifying memory locations needing
patches. Rather, the Specification broadly describes "[t]he step of
modifying a data word at the first location to a predetermined data value can
comprise modifying all of the data bit cells of the data word to a
programmed state" (Spec. 3: 10-11 ( emphasis added)). Moyer's Figure 2
and paragraph 24 ( expressly identified by the Examiner) similarly describe
modifying a memory data word ( data word of program memory 200 holding
patch code N-2) to a predetermined data value that is a programmed state
(programmed patch code N-2) (Final Act. 20-23 ( citing Moyer ,r 24, Fig.
2)). Thus, Moyer alone teaches or suggests "modifying the data word of the
plurality of data words at the first location [in the OTP memory where a
patch is required] to a predetermined data value" as recited in claim 1.
Appellant also argues a skilled artisan "would not have been
motivated to combine Kosaka's patching with the ROM in Moyer" (Reply
Br. 6; App. Br. 8). However, in light of our discussion supra, Moyer alone
teaches all limitations of Appellant's claim 1. A disclosure that anticipates
under 35 U.S.C. § 102 also renders the claim unpatentable under 35 U.S.C.
§ 103, for 'anticipation is the epitome of obviousness."' Connell v. Sears,
Roebuck & Co., 722 F.2d 1542, 1549 (Fed. Cir. 1983) (quoting In re
Fracalossi, 681 F.2d 792 (CCPA 1982)). We see no need to rely upon
Kosaka or the Examiner's rationale in combining the references to
demonstrate claim 1 's method would have been obvious to a person of
ordinary skill in the art. See In re Bush, 296 F.2d 491,496 (CCPA 1961)
(the Board may rely on less than all of the references applied by the
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Application 13/960,940
Examiner in an obviousness rationale without designating it as a new
ground); see also In re Kronig, 539 F.2d 1300, 1302---03 (CCPA 1976).
Thus, Appellant has failed to clearly distinguish the claimed invention
over the prior art relied on by the Examiner. We therefore sustain the
Examiner's rejection of independent claim 1, and dependent claims 2, 4, and
11 argued for their dependency from claim 1 (App. Br. 8-9, 13).
With respect to dependent claim 10, Appellant argues Moyer fails to
disclose "wherein the predetermined data value is a value associated with
each data bit cell of the plurality of the programmable data bit cells at the
first location being in a programmed state" (App. Br. 12). As discussed
supra with respect to claim 1, we are not persuaded Moyer's paragraph 24
and Figure 2 do not teach this feature. Further, Appellant argues limitations
that are narrower than the claim language, and are thus, not commensurate in
scope with claim 10 (App. Br. 12). Accordingly, we also sustain the
Examiner's rejection of claim 10.
Appellant further argues the "modifying" limitation in independent
claim 18 (App. Br. 15). Claim 18 recites the cumulative features of claims 1
and 10. We therefore sustain the Examiner's rejection of claim 18 for the
same reasons as claims 1 and 10.
Claims 3, 5-9, 19, and 20
Dependent claim 3 recites "the predetermined data value [ of the data
word in the OTP memory of claim 1] is a value of an exception instruction
of the processor which will cause the processor to read from the patch
table." The Examiner finds Moyer's paragraphs 31 and 33 and Kosaka's
column 15, lines 23-29 render claim 3 obvious (Ans. 84--86).
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Appellant argues an address comparison causes Moyer's processor to
read from a patch table, not a "value o(the data word" in the memory as
required by claim 3 (App. Br. 8-9). Thus, Moyer does not set a memory's
data word to "a value of an exception instruction of the processor" as
claimed (App. Br. 9). We agree with Appellant. Moyer does not use a value
of the memory's data words to trigger patching. Rather, Moyer uses address
comparators to compare reference addresses to a memory address and detect
if the memory address needs a patch identified via the patch table (see
Moyer ,r,r 28 ("each comparator is a maskable address comparator that
corresponds to an address or address range that triggers a memory
patch"), 3 0 ("if the match output from the 8th comparator is asserted, the
encoder may generate a 3-bit offset ... which uniquely identifies the 8th
comparator and provides an offset ... corresponding to the 8th location of the
patch pointer table")). Kosaka does not remedy Moyer's deficiency, as it
merely patches software code, not memory cells (App. Br. 9).
As the Examiner has not identified sufficient evidence to support the
rejection of claim 3, we do not sustain the Examiner's rejection of claim 3,
and claim 5 dependent therefrom.
Dependent claim 6 recites "modifying a data word at the first location
[in the OTP memory] to a predetermined data value further comprises
modifying subsequent data words at the first location to indicate a position
of the patch code location in the patch table." The Examiner finds Moyer's
paragraph 25 and Figure 2 and Kosaka' s column 15, lines 23-29 and column
17, lines 33-54 render claim 6 obvious (Ans. 88-89; Final Act. 39).
Appellant argues Moyer and Kosaka do not teach or suggest
"modifying subsequent data words at the first location to indicate a position
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of the patch code location in the patch table" (App. Br. 10). We agree with
Appellant. As discussed supra with respect to claim 3, Moyer and Kosaka
do not use a value of the memory's data words to trigger a patch table look
up. Rather, Moyer uses a memory address to indicate a location in the patch
table (see Moyer ,r 30). Therefore, we do not sustain the Examiner's
rejection of claim 6, and claims 7 and 8 dependent therefrom. We do not
address Appellant's additional arguments with respect to claims 7 and 8 as
the issues discussed supra are dispositive.
Dependent claim 9 recites "modifying subsequent data words at the
first location [in the OTP memory] to indicate the patch code location" by
programmed values of the memory's data words. As discussed supra with
respect to claims 3 and 6, Moyer and Kosaka do not use values of the
memory's data words to indicate location of patch codes. Rather, Moyer
uses memory addresses to indicate locations ( code pointers) in the patch
table (see Moyer ,r,r 28, 30, Fig. 2). Therefore, we do not sustain the
Examiner's rejection of claim 9.
Dependent claim 19 recites a system that "perform[ s] a look up in a
patch table for a patch code location" when "a value of the data word [ at a
first location in the OTP memory] corresponds to an exception instruction of
the processor." As discussed supra with respect to claim 3, we agree with
Appellant Moyer and Kosaka do not use a value of the memory's data words
to trigger a patch table look up. Therefore, we do not sustain the Examiner's
rejection of claim 19, and claim 20 dependent therefrom. We do not address
Appellant's additional argument with respect to claim 20 as the issues
discussed supra are dispositive.
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Claims 12 and 14
Independent claim 12 recites, inter alia, "determining if a value of the
data word corresponds to an exception instruction of the processor, the
exception instruction corresponding to the data value for all bits of the data
word at the first location being in a programmed state," and "if the value of
the data word is determined to correspond to the exception instruction ...
performing a look up in a patch table for a patch code location; and reading
data at the patch code location" ( emphasis added).
Appellant argues Moyer "fails to disclose triggering a redirection to
patch code based on the value of the data word at the address of an
instruction to be executed" (App. Br. 13). Appellant's argument is not
commensurate with the broadest reasonable interpretation of method claim
12, which does not require triggering a redirection to patch code based on a
data word value. Specifically, claim 12's "if' limitation is directed to a
conditional step, which recites performing actions (perform a look up in a
patch table for a patch code location, and read data at the patch code
location) only conditionally: that is, "if the value of the data word is
determined to correspond to the exception instruction." As such, the
broadest reasonable interpretation of claim 12 occurs when the conditional
limitation is not satisfied (i.e., when the data word value does not correspond
to the exception instruction). See Ex parte Schulhauser, Appeal No. 2013-
007847, 2016 WL 6277792 (PTAB Apr. 28, 2016) (precedential). Thus,
"performing a look up in a patch table for a patch code location" and
"reading data at the patch code location" may never occur if the conditional
limitation is not satisfied.
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With respect to the non-conditional portion of claim 12 ("determining
if a value of the data word corresponds to an exception instruction of the
processor"), we agree with the Examiner Moyer suggests this limitation
(Final Act. 56-58; see Moyer ,r,r 3, 41). Kosaka also discloses it is known to
check a data word's correlation to an exception instruction, where the data
word may be a software-set value (see Kosaka col. 15, 11. 24--29, col. 22, 11.
42--44).
In light of the conditional limitations recited in claim 12 and the
arguments presented, Appellant has failed to clearly distinguish the claimed
invention over the prior art relied on by the Examiner. We therefore sustain
the Examiner's rejection of independent claim 12, and dependent claim 14
argued for its dependency from claim 12 (App. Br. 14).
Claims 13 and 15-17
Dependent claim 13 depends from claim 12 and further recites
"performing a logical operation on the data word read from the first location
in the one time programmable memory to form a mapped value" and
"applying the mapped value to the processor" to determine if the mapped
data word value corresponds to a processor exception instruction.
The Examiner finds Moyer's paragraphs 13, 22-24, and 31 render
claim 13 obvious (Ans. 100; Final Act. 70-74). Appellant argues "Moyer
merely disclose[ s] the use of comparators and a patch pointer table to
redirect execution flow to patch code" but Moyer or Kosaka do not teach or
suggest "'performing a logical operation' on this word [read from a location
in the OPT memory] to 'form a mapped value' that corresponds to the
exception," as claimed (App. Br. 14).
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We agree with Appellant. Moyer's patch pointers and "address mask
... used to map to ... entries in patch pointer table" perform logical
operations on memory addresses, not on a data word read from an OTP
memory to form a mapped value as claimed (see Moyer ,r,r 30-31, 33).
Kosaka does not remedy Moyer's deficiency, as it does not disclose
performing a logical mapping operation on data words read from an OTP
memory. Therefore, we do not sustain the Examiner's rejection of claim 13.
Claim 15 depends from claim 12 and further requires "reading
subsequent data words at the first location [in the one time programmable
memory] to determine a position of the patch code location in the patch
table." As discussed supra with respect to claim 6, we agree with Appellant
Moyer and Kosaka do not use values of the memory 's data words to
determine a position of a patch code location in a patch table. Rather,
Moyer uses a memory address to determine a position in a patch table (see
Moyer ,r 30). Therefore, we do not sustain the Examiner's rejection of claim
15, and claims 16 and 17 dependent therefrom. We do not address
Appellant's additional argument with respect to claims 16 and 17 as the
issues discussed supra are dispositive.
DECISION
The Examiner's decision rejecting claims 1, 2, 4, 10, 11, 12, 14, and
18 under 35 U.S.C. § 103 is affirmed.
The Examiner's decision rejecting claims 3, 5-9, 13, 15-17, 19, and
20 under 35 U.S.C. § 103 is reversed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
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Application 13/960,940
AFFIRMED-IN-PART
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