Ex Parte Hepner et al

Board of Patent Appeals and Interferences

Apr 27, 2009

10163288 (B.P.A.I. Apr. 27, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
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Ex parte DAVID FRANK HEPNER and ANDREW DALE WALLS
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Appeal 2008-3262
Application 10/163,288
Technology Center 2100
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Decided:1 April 27, 2009
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Before JOHN C. MARTIN, LANCE LEONARD BARRY, and
CAROLYN D. THOMAS, Administrative Patent Judges.

BARRY, Administrative Patent Judge.

DECISION ON APPEAL

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail date (paper delivery) or Notification Date (electronic Delivery).
Appeal 2008-3262
Application 10/163,288

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STATEMENT OF THE CASE
The Patent Examiner rejected claims 1-21. The Appellants appeal
therefrom under 35 U.S.C. § 134(a). We have jurisdiction under 35 U.S.C.
§ 6(b).
INVENTION
The invention at issue on appeal effects parallel execution of related
or dependent direct memory access ("DMA") transfers. (Spec. 6.)

ILLUSTRATIVE CLAIM
1. A method for chaining and overlapping DMA transfers, the
method comprising:
detecting access to a memory location within a memory
block corresponding to a first DMA transfer; and
concurrently conducting a second DMA transfer in
response to detecting access to the memory location within the
memory block corresponding to the first DMA transfer.

PRIOR ART
Peterson 6,678,755 B1 Jan. 13, 2004
Nahidipour 5,938,743 Aug. 17, 1999

REJECTIONS
Claims 1 and 3-21 stand rejected under 35 U.S.C. § 102(e) as being
anticipated by Peterson.

Claim 2 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Peterson and Nahidipour.
Appeal 2008-3262
Application 10/163,288

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ISSUE
"Rather than reiterate the positions of the parties in toto, we focus on
an issue therebetween." Ex parte Kuruoglu, No. 2007-0666, 2007 WL
2745820, at *2 (BPAI 2007). The Examiner finds that in "Peterson: col. 4,
lines 1-10" (Supp. Answer 3) "the 'Address field' or alternatively 'Address
bus' is used for the purpose of 'detecting access to a memory location within
a memory block corresponding to a first DMA transfer'" (id.) The
Appellants argue that "at most, Peterson teaches detecting access to the
address of the DMA command and not a memory location within a memory
block corresponding to the first DMA transfer." (2d Reply Br. 6.)
Therefore, the issue before us is whether the Appellants have shown error in
the Examiner's finding that Peterson detects access to a memory location
within a memory block corresponding to a first DMA transfer.

LAW
"[A]nticipation of a claim under § 102 can be found only if the prior
art reference discloses every element of the claim . . . ." In re King, 801
F.2d 1324, 1326 (Fed. Cir. 1986) (citing Lindemann Maschinenfabrik
GMBH v. American Hoist & Derrick Co., 730 F.2d 1452, 1457 (Fed. Cir.
1984)). "[A]bsence from the reference of any claimed element negates
anticipation." Kloster Speedsteel AB v. Crucible, Inc., 793 F.2d 1565, 1571
(Fed. Cir. 1986).

Appeal 2008-3262
Application 10/163,288

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FINDINGS OF FACT ("FFs")
1. Peterson's "DMA controller 101 . . . executes DMA operations that
are specified by command pairs in a chained DMA command list." (Col. 3,
ll. 18-20.)

2. "Each DMA command pair consists of an Address field in the even
dword and a Length field in the odd dword." (Id. ll. 24-26.) "The Address
field provides a word-aligned physical byte address of either: 1) the first
dword of data in the data array 26 that is to be accessed for that command, or
2) the (link) address of the next DMA command to be executed." (Id. ll. 28-
31.)

3. "In one embodiment, the DMA controller 101 is commanded to
pause when the link address matches the address of the most recent DMA
command, that is, a self-pointing link address. In another embodiment, the
DMA controller pauses when the link address matches a predetermined
code." (Id. ll. 62-67.)

4. The part of the reference relied on by the Examiner follows.
The DMA controller will subsequently periodically check the
Address field of the most recent DMA command for a new
address for the next DMA command to be executed. When a
new value is provided by the Address field, the DMA
controller 101 will proceed to execute the appended DMA
commands located at the address. Alternatively, the DMA
controller 101 may monitor an address bus for access to the
address of the DMA command having the self-linking address,
Appeal 2008-3262
Application 10/163,288

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instead of periodically checking for changes in the value of the
Address field.
(Col. 3, l. 67 – col. 4, l. 10.)

ANALYSIS
The independent claims require detecting access to a memory location
within a memory block corresponding to a first DMA transfer. In contrast,
Peterson's DMA controller detects a link address of the next DMA command
to be executed. (FF 4.) Therefore, we agree with the Appellants that the
reference "teaches detecting access to the address of the DMA command
and not a memory location within a memory block corresponding to the first
DMA transfer." (2d Reply Br. 6.) The Examiner does not allege, let alone
show, that the addition of Nahidipour cures the aforementioned deficiency of
Peterson.

CONCLUSION
Based on the aforementioned facts and analysis, we conclude that the
Appellants have shown error in the Examiner's finding that Peterson detects
access to a memory location within a memory block corresponding to a first
DMA transfer.

DECISION
We reversed the rejections of claims 1-21.

REVERSED

Appeal 2008-3262
Application 10/163,288

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