Ex Parte Henderson

Board of Patent Appeals and Interferences

May 17, 2010

10405904 (B.P.A.I. May. 17, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
_____________

Ex parte ROBERT K. HENDERSON
_____________

Appeal 2009-004652
Application 10/405,904
Technology Center 2600
______________

Decided: May 17, 2010
_______________

Before, ROBERT E. NAPPI, JOHN C. MARTIN, and
JOSEPH F. RUGGIERO, Administrative Patent Judges.

NAPPI, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2009-004652
Application 10/405,904

This is a decision on appeal under 35 U.S.C. § 134(a) of the final
rejection of claims 10-14, 16-21, 23-25, and 28-30.1 We have jurisdiction
under 35 U.S.C. § 6(b).
We affirm.

INVENTION
The invention is directed to an image sensor with a readout circuit that
stores the values in a memory. These values are subsequently subtracted
from corresponding signal values to reduce kT/C and fixed pattern noise.
See Spec: 1-2. Claim 10 is representative of the invention and reproduced
below:
10. An image array sensor comprising:
an array of pixels arranged in rows and columns, each pixel
comprising a light-sensitive element and switching means for
applying a reset signal to the pixel and to read out a pixel signal
from the pixel;
a dual mode common integrated read-reset circuit, in each
column, to operate as a buffer in a first mode to apply the reset
signal to the pixels, and to also operate as a comparator in a
second mode to read pixel reset signals and pixel signals;
analog-to-digital conversion means for converting the pixel
reset signals and the pixel signals from analog to digital; and
a memory to store the digital pixel reset signals of the pixels
for up to a complete frame.

1 Claims 1-9 were cancelled in a Preliminary Amendment filed April 2,
2003. Claims 15, 22, and 26-27 were cancelled in response to a Non-Final
Office Action mailed June 2, 2006.
2
Appeal 2009-004652
Application 10/405,904

REFERENCES
Tandon US 5,153,421 Oct. 6, 1992

Yang US 6,362,767 B1 Mar. 26, 2002

Krymski US 6,809,766 B1 Oct. 26, 2004
(filed Jan. 31, 2001)

Boemler US 6,965,407 B2 Nov. 15, 2005
(filed Mar. 25, 2002)

REJECTIONS AT ISSUE
Claims 10-14, 16-21, 23-25, and 28-30 are rejected under 35 U.S.C.
§ 112, first paragraph, as failing to comply with the written description
requirement. Ans. 3.2
Claims 10, 11, 14, 17-18, and 21 are rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Boemler in view of Tandon. Ans. 3-6.
Claims 12-13 and 19-20 are rejected under 35 U.S.C. § 103(a) as
being unpatentable over Boemler in view of Tandon and Yang. Ans. 7-8.
Claims 24 and 25 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Boemler in view of Tandon and Krymski. Ans. 8-10.
Claims 16 and 23 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Boemler in view of Tandon. Ans. 10-11.

2 The Examiner mistakenly included claims 15, 22, and 26-27 in the 35
U.S.C. § 112, first paragraph, rejection. These claims have been cancelled
by Appellant and are therefore not included in this rejection.
3
Appeal 2009-004652
Application 10/405,904

ISSUES
35 U.S.C. § 112, first paragraph, rejection
Appellant argues on pages 8-9 of the Appeal Brief that the Examiner’s
rejection of claims 10-14, 16-21, 23-25, and 28-30 under 35 U.S.C. § 112,
first paragraph, is in error. Appellant argues that the Specification supports
the term “dual mode common integrated read-reset circuit.” App. Br. 8.
Thus, Appellant’s contention with respect to claims 10-14, 16-21, 23-
25, and 28-30 present us with the issue: Did the Examiner err in finding that
the Specification does not provide adequate support for the term “dual
common integrated read-reset circuit,” as recited in each of the independent
claims?
35 U.S.C. § 103(a) rejections
Appellant argues on page 10-13 of the Appeal Brief that the
Examiner’s rejection of claims 10 and 17 is in error. Appellant argues that
none of the references disclose “a dual mode common integrated read-reset
circuit” as found in claims 10 and 17. App. Br. 12. Appellant also argues
that the Examiner has not provided sufficient motivation to combine the
references. Additionally, Appellant argues on pages 14-15 of the Appeal
Brief that the Examiner’s rejection of claims 12-13, 16, 19-20, and 23-25 is
in error for the same reasons as claims 10 and 17.
Thus, Appellant’s arguments with respect to the Examiner’s rejection
of claims 10 and 17 and claims 12-13, 16, 19-20, and 23-25 present us with
two issues: (1) Did the Examiner err in finding that the references disclose a
dual mode common integrated read-reset circuit? (2) Did the Examiner
provide a proper motivation to combine the references?

4
Appeal 2009-004652
Application 10/405,904

ANALYSIS
35 U.S.C. § 112, first paragraph, rejection

Appellant’s contentions have not persuaded us of error in the
Examiner’s rejection of claims 10-14, 16-21, 23-25, and 28-30 under 35
U.S.C. § 112, first paragraph. Independent claims 10, 17, 24, and 28 each
contain the limitation “a dual mode common integrated read-reset circuit.”
Claims 11-14, 16, 18-21, 23, 25-27, and 29-30 ultimately depend upon
claims 10, 17, 24, and 28 and therefore incorporate the above recited
limitation. Appellant argues that Appellant’s patent application, including
the Specification and Drawings, disclose an integrated circuit. App. Br. 8.
Appellant points to Figures 1 and 2 of Appellant’s drawings, reference
numeral 22, the Read-Reset Amplifier (RRComp), to show that the circuit is
integrated. App. Br. 8-9. Additionally, Appellant points to page 3, lines 19-
30, of Appellant’s Specification to show that the RRComp has two different
modes. App. Br. 8-9. We agree with Appellant that the Specification
defines the RRComp as having two separate modes. However, we do not
find that simply showing a circuit as a box equates to an integrated circuit.
Without further evidence, we do not find Appellant’s argument to be
persuasive and we sustain the Examiner’s rejection of claims 10-14, 16-21,
23-25, and 28-30 under 35 U.S.C. § 112, first paragraph.
35 U.S.C. § 103(a) rejections
Appellant’s contentions have not persuaded us of error in the
Examiner’s rejection of claims 10-14, 16-21, 23-25, and 28-30 under 35
U.S.C. § 103(a). Appellant argues that neither Boemler nor Tandon disclose
a dual mode common integrated read-reset circuit. App. Br. 12. Appellant
5
Appeal 2009-004652
Application 10/405,904

admits that both of the references disclose a read circuit and a reset circuit.
App. Br. 12. However, Appellant argues that both references disclose these
circuits as discrete circuitry, i.e., separate components, and not as an
integrated circuit. App. Br. 12. We note that making elements of a device
integral or separable is considered to be an obvious design choice and does
not render an invention patentable. See In re Larson, 340 F.2d 965, 968
(CCPA 1965); In re Dulberg, 289 F.2d 522, 523 (CCPA 1961). Thus,
combining each of these elements into a single unit represents nothing more
than a combination of known devices, which when combined yield the
predictable result of an integrated read-reset circuit. KSR Int’l v. Telefle,
Inc., 550 U.S. 398, 416 (2007). As such, we find that the Examiner did not
err in finding that Boemler in view of Tandon discloses or suggests a dual
mode common integrated read-reset circuit.
In addition, Appellant argues that the Examiner’s motivation to
combine the references is improper. App. Br. 13. The Examiner finds that
Boemler discloses a read and a reset circuit as two separate components.
Ans. 4. The Examiner also finds that Tandon discloses combining multiple
circuits on one device as an integrated circuit. Ans. 4. Therefore, the
motivation to combine Tandon’s teaching with Boemler’s components is to
reduce the number of chips that need to be handled. Ans. 4. Appellant
states that Boemler’s amplifier and comparator are already combined on a
single chip to form a single solid state imager. App. Br. 13. As such it
appears that the Appellant is equating an integrated circuit as being on a
chip. Based upon this, Appellant argues that one of ordinary skill would not
have been motivated to modify Boemler. App. Br. 13. Thus, Appellant
seems to be arguing that the Examiner’s motivation is improper because
6
Appeal 2009-004652
Application 10/405,904

Boemler’s entire imager device is on one integrated chip and it would not
make sense to combine just the amplifier and comparator on a single chip.
We note that the Examiner did not find that Boemler discloses that the
amplifier and comparator are disclosed on a single chip, and Appellant has
not provided a citation to support the statement that they are. Nonetheless, it
is an admission by Appellant that Boemler teaches that both circuits are on a
single chip. Thus, it would seem that Appellant is admitting that Boemler
teaches the claimed feature of the two circuits being part of an integrated
circuit. Regardless, as noted above, combining devices or separating devices
is an obvious design choice. See Larson, 340 F.2d at 968; Dulberg, 289
F.2d at 523. Therefore Appellant has not persuaded us that the Examiner
erred in combining the teachings of Tandon and Boemler.
As such, we sustain the Examiner’s rejection of claims 10-14, 16-21,
23-25, and 28-30 for the reasons discussed supra.

CONCLUSION
The Examiner did not err in finding that the Specification does not
provide adequate support for the term “dual common integrated read-reset
circuit,” as recited in each of the independent claims.
The Examiner did not err in finding that the references disclose or
suggest a dual mode common integrated read-reset circuit.
The Examiner did provide a proper motivation to combine the
references.

7
Appeal 2009-004652
Application 10/405,904

SUMMARY
The Examiner’s decision to reject claims 10-14, 16-21, 23-25, and 28-
30 under 35 U.S.C. § 112, first paragraph, is affirmed.
The Examiner’s decision to reject claims 10-14, 16-21, 23-25, and 28-
30 under 35 U.S.C. § 103(a) is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136 (a)(1)(iv).
8
Appeal 2009-004652
Application 10/405,904

AFFIRMED

ELD

ALLEN, DYER, DOPPELT, MILBRATH & GILCHRIST P.A.
1401 CITRUS CENTER 255 SOUTH ORANGE AVENUE
P.O. BOX 3791
ORLANDO, FL 32802-3791
9