Ex Parte Havin et al

Patent Trial and Appeal Board

Apr 21, 2014

11964684 (P.T.A.B. Apr. 21, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte VICTOR HAVIN and JONATHAN M. SANDERS1
____________________

Appeal 2011-008943
Application 11/964,684
Technology Center 2100
____________________

Before JEAN R. HOMERE, JOHNNY A. KUMAR, and LARRY J. HUME,
Administrative Patent Judges.

HUME, Administrative Patent Judge.

DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) of the Final
Rejection of claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.

1 The Real Party in Interest is International Business Machines Corporation.
App. Br. 4.
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STATEMENT OF THE CASE2
The Invention
Appellants’ invention relates to a processor and storage medium
including microcode therein that performs runtime analysis, and
instrumented microcode that (1) monitors at least one execution of a
machine instruction resulting in a memory access, (2) accesses at least one
memory state indicator to determine whether the memory access is
improper, and (3) outputs an exception when the memory access is
improper. Abstract.
Exemplary Claims
Claims 1, 3, 4, 6, and 15, reproduced below, are representative of the
subject matter on appeal (emphases added):
1. A processor, comprising:
a storage medium within the processor comprising
microcode stored thereon that performs runtime analysis, the
storage medium comprising:
instrumented microcode that monitors at least one
execution of a machine instruction resulting in a memory
access;
instrumented microcode that accesses at least one
memory state indicator to determine whether the memory
access is improper; and

2 Our decision refers to Appellants’ Appeal Brief (“App. Br.,” filed
Dec. 28, 2010); Reply Brief (“Reply Br.,” filed Apr. 7, 2011); Examiner’s
Answer (“Ans.,” mailed Feb. 7, 2011); Final Office Action (“FOA,” mailed
June 30, 2010); and the original Specification (“Spec.,” filed Dec. 26, 2007).
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instrumented microcode that outputs an exception when
the memory access is improper.
3. The processor of claim 1, wherein:
the instrumented microcode that accesses at least one
memory state indicator to determine whether the memory
access is improper comprises:
instrumented microcode that fetches data from a
first register;
instrumented microcode that fetches a memory
address from a second register; and
instrumented microcode that fetches the memory
state indicator from a location in a state memory that
corresponds to the memory address; and
the instrumented microcode that outputs an exception
comprises:
instrumented microcode that selectively generates
the exception when the memory state indicator indicates
that the memory address is unallocated or trapped.
4. The processor of claim 1, wherein:
the instrumented microcode that accesses at least one
memory state indicator to determine whether the memory
access is improper comprises:
instrumented microcode that fetches data from a
first register;
instrumented microcode that fetches a memory
address from a second register; and
instrumented microcode that fetches the memory
state indicator from a location in a state memory that
corresponds to the memory address; and
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the storage medium further comprises:
instrumented microcode that selectively changes
the memory state indicator if the memory state indicator
indicates that the memory address is allocated but
uninitialized.
6. The processor of claim 1, wherein the storage
medium further comprises:
instrumented microcode that reserves a range of system
memory for use as a state memory in which the at least one
memory state indicator is stored.
15. A computer program product comprising:
a computer readable storage medium having stored
thereon computer readable program code that configures a
processor to provide runtime error detection, the computer
readable storage medium comprising:
computer readable program code that configures
the processor to monitor at least one execution of a
machine instruction resulting in a memory access;
computer readable program code that configures
the processor to access at least one memory state
indicator to determine whether the memory access is
improper; and
computer readable program code that configures
the processor to output an exception when the memory
access is improper.

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Prior Art
The Examiner relies upon the following prior art in rejecting the
claims on appeal:
Flory US 5,910,180 Jun. 8, 1999
Reiser US 6,718,485 B1 Apr. 6, 2004
Agarwal et al., ATUM: A New Technology for Capturing
Address Traces Using Microcode, ACM SIGARCH
Computer Architecture News, Vol. 14, Issue 2 (May
1986); Special Issue: Proceedings of the 13th annual
international symposium on Computer Architecture (ISC
‘86), pp. 119-127 (hereinafter “Agarwal”).
Sites et al., Multiprocessor Cache Analysis Using ATUM,
ACM SIGARCH Computer Architecture News, Vol. 16,
Issue 2 (May 1988), pp. 186-195, 1988 (hereinafter
“Sites”).
Rejections on Appeal
1. Claims 15-20 stand rejected under 35 U.S.C. § 101 as being
directed to non-statutory subject matter. Ans. 4.
2. Claims 1, 3-6, 8, 10-13, 15, and 17-20 stand rejected under
35 U.S.C. § 103(a) as being unpatentable over the combination of Reiser and
Agarwal. Ans. 5.
3. Claims 2, 9, and 16 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over the combination of Reiser, Agarwal, and Flory.
Ans. 21.
4. Claims 7 and 14 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over the combination of Reiser, Agarwal, and Sites.
Ans. 23.
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CLAIM GROUPING
Based upon Appellants’ arguments over the common unpatentability
rejection of claims 1, 3-6, 8, 10-13, 15, and 17-20 in view of Reiser and
Agarwal (App. Br. 12 et seq), we select the following claim grouping to
decide this Appeal:
A. Group A: Claims 1, 8, and 15 stand or fall with independent
claim 1.
B. Group B: Claims 3, 10, and 17 stand or fall with dependent
claim 3.
C. Group C: Claims 4, 5, 11, 12, 18, and 19 stand or fall with
dependent claim 4.
D. Group D: Claims 6, 13, and 20 stand or fall with dependent
claim 6.
The Examiner separately rejected claims 2, 9, and 16 under § 103 over
the combination of Reiser, Agarwal, and Flory, and claims 7 and 14 under
§ 103 over the combination of Reiser, Agarwal, and Sites. However,
Appellants did not separately argue these rejections. App. Br. 27-29.
Instead, Appellants merely rely upon the arguments presented with respect
to their respective independent claims, as discussed infra.
ISSUES AND ANALYSIS
We only consider those arguments actually made by Appellants in
reaching this decision, and we do not consider arguments which Appellants
could have made but chose not to make in the Briefs so that any such
arguments are deemed to be waived. 37 C.F.R. § 41.37(c)(1)(vii).
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We disagree with Appellants’ conclusions with respect to claims 1-20,
and we adopt as our own (1) the findings and reasons set forth by the
Examiner in the action from which this appeal is taken and (2) the reasons
and rebuttals set forth by the Examiner in the Examiner’s Answer in
response to Appellants’ Arguments. However, we highlight and address
specific findings and arguments regarding claims 1, 3, 4, 6, and 15 for
emphasis as follows.
1. Non-Statutory Subject Matter Rejection of Claims 15-20
Issue 1
Appellants argue (App. Br. 11, 12; Reply Br. 5-16) the Examiner’s
rejection of claims 15-20 under 35 U.S.C. § 101 as being directed to non-
statutory subject matter is in error. These contentions present us with the
following issue:
Did the Examiner err in finding that the recitation in claim 15 of
“computer readable storage medium having stored thereon computer
readable program code” reads on transitory media, including a propagating
signal?
Analysis
Appellants contend, “since the functional descriptive material is
recorded on the computer readable storage medium, it necessarily follows
that the computer readable storage medium is non-transitory in nature. In
other words, a transitory signal merely propagates information, but does not
store the information.” App. Br. 12.
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In their Reply, Appellants summarize their arguments by contending,
“a proper claim construction of the term ‘computer usable [sic] storage
medium’ does not encompass a transitory, propagating signal . . . [but is
instead] at least a manufacture . . . [such that] the rejection of claims 15-20
under 35 U.S.C. § 101 is not proper and should be withdrawn.” Reply
Br. 16.
We note Appellants’ Specification does not limit the storage medium
to non-transitory forms, i.e.,
Any suitable computer-usable or computer-readable medium
may be utilized. For example, the medium can include, but is
not limited to, an electronic, magnetic, optical, magneto-optical,
electromagnetic, infrared, or semiconductor system (or
apparatus or device), or a propagation medium.
Spec. ¶ [0011]. Notwithstanding recitation of the additional word “storage”
in the limitation in dispute, we agree with the Examiner (Ans. 27), and find
the scope of the recited “computer readable storage medium” encompasses
transitory media such as signals or carrier waves.
Under our jurisprudence, the scope of the recited “computer readable
storage medium” encompasses transitory media such as signals or carrier
waves, where, as here, the Specification does not limit the computer
readable storage to non-transitory forms. Ex parte Mewherter, 107 USPQ2d
1857 (PTAB 2013) (precedential) (holding recited machine-readable storage
medium ineligible under § 101 because it encompasses transitory media).
Here, the recited “computer readable storage medium” is not claimed as
non-transitory, and the disclosure does not expressly and unambiguously
limit that medium to solely non-transitory forms via a definition or similar
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limiting language. Therefore, the medium encompasses transitory forms and
is ineligible under § 101.
Accordingly, Appellants have not provided sufficient evidence or
argument to persuade us of any reversible error in the Examiner’s statutory
subject matter rejection of claims 15-20, which we sustain.
2. Unpatentability Rejection of Claims 1, 8, and 15
Issue 2
Appellants argue (App. Br. 12-15; Reply Br. 16) the Examiner’s
rejection of claims 1, 8, and 15 under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Reiser and Agarwal is in error. These
contentions present us with the following issues:
(a) Did the Examiner err in finding the cited prior art combination
teaches or suggests the limitation of “instrumented microcode that outputs
an exception when the memory access is improper,” as recited in claim 1?
(b) Did the Examiner err in finding proper motivation to combine
Reiser and Agarwal in the manner suggested because “[a]bsent hindsight
reasoning based on the teachings contained in Appellants’ specification, one
skilled in the art [of] using software emulation would not look to teachings
in hardware microcode to overcome the problems overcome by Appellants’
invention” (App. Br. 13)?
Analysis
Issue 2(a)
Appellants contend Agarwal uses microcode “merely to capture
address traces in a reserved part of main memory as a side effect of normal
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operation” and, therefore, “microcode functionality is nothing more than that
of a Scribner [which] merely copies data for later analysis, but is unaware of
different aspects of the usage of the data.” Id. (citing Agarwal Abstract;
p. 120, ll. 3-7, (§“Tracing Using Microcode”)).
Appellants particularly contend:
[A]n exception is triggered by instrumented microcode when
the memory access is improper. To generate an exception (i.e.,
interrupt), the exception must be communicated from the
microcode layer to another system layer (e.g., communicated to
an operating system, driver or application layer). Appellants’
specification at pg. 10, lines 9-14. Neither Reiser nor Agarwal
disclose or suggest Appellants’ recited exception.
App. Br. 14.
We find the Examiner has relied upon the combined teachings and
suggestions of Reiser and Agarwal, but Appellants’ arguments focus almost
exclusively on the purported deficiencies of Agarwal, as cited above. The
Examiner relies upon Reiser for teaching all the functional limitations of
claim 1 recited as being performed by the claimed processor, except that
Reiser does not teach the use of microcode stored in a storage medium,
which is used to carry out the recited functions. Instead, the Examiner relies
upon Agarwal for teaching or suggesting the use of microcode stored in a
storage medium to carry out memory analysis.
Ans. 5, 6.
In agreement with the Examiner, we find Reiser teaches analysis of
memory references by a tracing technique using software emulation
hardware. See generally Reiser, Abstract. We also find Reiser teaches all
the functional limitations of claim 1 claimed as being performed by the
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processor, i.e., “perform[ing] runtime analysis . . . monitor[ing] at least one
execution of a machine instruction resulting in a memory access; access[ing]
at least one memory state indicator to determine whether the memory access
is improper; and output[ting] an exception . . . .” See Reiser col. 1, ll. 59-60,
col. 2, ll. 62-64, col. 4, ll. 15-23, and col. 8, ll. 17-19. In further agreement
with the Examiner, we also find Agarwal teaches or suggests performing
runtime analysis of memory references using a microcode implementation
for memory studies. See Agarwal p. 119 (“Abstract” and “Introduction”),
p. 120 (“Tracing Using Microcode”), p. 122 (“An Experimental
Implementation”).
As for the recited “exception” argued by Appellants, Reiser teaches or
suggests:
When the tool detects improper behavior, the tool issues
an error message identifying the kind of error and where it
occurred. Improper behavior may be any access to a logically
unallocated region, or a read (or modify) access to bytes which
have been allocated but not yet written.
Reiser col. 2, ll. 62-66. We find this discussion in Reiser teaches or suggests
outputting an exception when memory access in improper. See Ans. 34.
Further, we find Appellants’ arguments are not commensurate with
the scope of claim 1. For example, Appellants further contend, in purported
contrast to the teachings of Agarwal, “claim 1 is directed to usage of
microcode in a way that the microcode is aware of memory usage and other
features that typically are only dealt with at the operating system or
application level” (App. Br. 13), while “Agarwal’s microcode is not aware
of whether an application’s use of memory is proper or improper. Instead,
the memory traces generated by Agarwal are captured for later analysis.” Id.
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Contrary to Appellants’ arguments, we find claim 1 does not
distinguish memory usage or other features dealt with at the operating
system or application level from any other level. Appellants’ contentions do
not persuade us of error on the part of the Examiner because Appellants are
responding to the rejection by attacking the references separately, even
though the rejection is based on the combined teachings of the references.
Nonobviousness cannot be established by attacking the references
individually when the rejection is predicated upon a combination of prior art
disclosures. See In re Merck & Co. Inc., 800 F.2d 1091, 1097 (Fed. Cir.
1986).
Accordingly, we agree with the Examiner’s findings (Ans. 5, 6) that
the combination of Reiser and Agarwal teaches or suggests all the
limitations of claim 1.
Issue 2(b)
Appellants contend “[a]bsent hindsight reasoning based on the
teachings contained in Appellants’ specification, one skilled in the art using
software emulation would not look to teachings in hardware microcode to
overcome the problems overcome by Appellants’ invention.” App. Br. 13.
Appellants further contend:
[A] person developing an application or operating system
generally is not the same person developing microcode.
Microcode is fundamentally different that software. Indeed,
Microcode is a layer of hardware-level instructions within a
processor, and thus implemented by hardware designers. In this
regard, a microcode developer is familiar with the architecture
of a processor beyond what is typically revealed to the outside
world. Those skilled in the art of software development
generally are not familiar with implementing microcode.
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Instead, software developers generally rely on high level
programming languages.
App. Br. 14 (footnote omitted). Appellants’ arguments, which attempt to
redefine and narrow the scope of the related art, and thereby limit the
presumed knowledge of a person of ordinary skill in the art, do not persuade
us of Examiner error in combining the cited prior art in the manner
suggested.
We find the references represent the level of ordinary skill in the art,
with Reiser teaching (see Abstract) a software emulation approach for
analyzing memory references of a computer program, and Agarwal teaching
(see Abstract) trace-driven simulation (TDS) for memory studies using a
microcode implementation. See In re GPAC Inc., 57 F.3d 1573, 1579 (Fed.
Cir. 1995) (finding the Board of Patent Appeals and Interference did not err
in concluding the level of ordinary skill was best determined by the
references of record); In re Oelrich, 579 F.2d 86, 91 (CCPA 1978) (“[T]he
PTO usually must evaluate . . . the level of ordinary skill solely on the cold
words of the literature.”). “‘Every patent application and reference relies to
some extent upon knowledge of persons skilled in the art to complement that
disclosed . . . .’” In re Bode, 550 F.2d 656, 660 (CCPA 1977) (quoting In re
Wiggins, 488 F.2d 538, 543 (CCPA 1973)). Those persons “must be
presumed to know something” about the art “apart from what the references
disclose.” In re Jacoby, 309 F.2d 513, 516 (CCPA 1962).
Accordingly, Appellants have not provided sufficient evidence or
argument to persuade us of any reversible error in the Examiner’s reading of
the contested limitations on the cited prior art, or in combining the
references in the manner suggested. Therefore, we sustain the Examiner’s
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obviousness rejection of independent claim 1. As Appellants have not
provided separate, substantive arguments with respect to independent claims
8 and 15, rejected on the same basis as claim 1, we similarly sustain the
Examiner’s rejection of these claims under 35 U.S.C. § 103(a).
§ 103(a) Rejection of Claims 2, 9, and 16
Claims 2, 9, and 16 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Reiser, Agarwal, and Flory.
Appellants merely argue, “[f]or reasons that should be clear from the
discussion . . . with respect to claim 1, rather than triggering an exception
from the microcode, Agarwal discloses that the microcode is modified to
record addresses of memory references, but control of a tracing mechanism
is provided from a high level computer program.” App. Br. 27. Appellants
also allege “for reasons that should be clear from the discussion of Agarwal
set forth above with respect to claim 1, Reiser and Agarwal are not properly
combinable to sustain the rejection of claim 83 under 35 U.S.C. § 103.”
App. Br. 28 (emphasis added).
In view of the lack of any substantive or separate arguments directed
to the unpatentability rejection of claims 2, 9, and 16 under § 103, as cited,
supra, we sustain the Examiner’s unpatentability rejection of these claims,
as they fall with their respective independent claims 1, 8, and 15. When the
patentability of dependent claims is not substantively argued separately, the
claims stand or fall with the claims from which they depend. In re King, 801
F.2d 1324, 1325 (Fed. Cir. 1986); In re Sernaker, 702 F.2d 989, 991 (Fed.

3 We note the apparent typographical error, and take this misstatement to
have been intended to state “claim 1.”
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Cir. 1983). Therefore, we sustain the Examiner’s rejection of claims 2, 9,
and 16.
§ 103(a) Rejection of Claims 7 and 14
Claims 7 and 14 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Reiser, Agarwal, and Sites.
Appellants merely allege, “[c]laims 7 and 14 are believed to be in condition
for allowance at least based upon their dependence on allowable underlying
base claims.” App. Br. 29. Thus, we find these claims fall with their
respective independent claims 1 and 8. See In re King, 801 F.2d at 1325 and
In re Sernaker, 702 F.2d at 991. Therefore, we sustain the Examiner’s
rejection of claims 7 and 14.
3. Unpatentability Rejection of Claims 3, 10, and 17
Issue 3
Appellants argue (App. Br. 17-18) the Examiner’s rejection of claim 3
under 35 U.S.C. § 103(a) as being unpatentable over the combination of
Reiser and Agarwal is in error. These contentions present us with the
following issue:
Did the Examiner err in finding the cited prior art combination teaches
or suggests the instrumented microcode that outputs an exception includes
“instrumented microcode that selectively generates the exception when the
memory state indicator indicates that the memory address is unallocated or
trapped,” as recited in dependent claim 3?
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Analysis
Appellants contend the passage of Reiser cited by the Examiner (FOA
4-6 (citing Reiser col. 8, ll. 17-19)) teaches information is used to consult
and update a table of memory states for each address in the memory space,
but that such consulting and updating is performed by a software tool which
purportedly is not synonymous with Appellants’ recited “instrumented
microcode” because “Software and microcode are distinctly different.” App.
Br. 17, 18 (citing Reiser col. 2, ll. 40, 41; col. 8, ll. 1-2, and ll. 17-19).
Appellants further contend:
Nowhere does Agarwal disclose or suggest that microcode is
patched to selectively generate the exception when the memory
state indicator indicates that the memory address is unallocated
or trapped. In this regard, Agarwal’s microcode captures
address traces, but is not aware of whether the memory address
is unallocated or trapped. Moreover, Agarwal’s microcode
does not include decision processes based on these conditions.
Instead, such awareness and decision processes typically occur
at the operating system or application level.
App. Br. 18. We find Appellants’ arguments with respect to dependent
claim 3 are substantially the same as those presented with respect to
independent claim 1, discussed supra. In response, the Examiner finds
(Ans. 6-8), and we agree, neither Reiser nor Agarwal are relied upon
individually to teach or suggest the overall limitations. Instead, Reiser
teaches the limitations regarding awareness of whether the memory address
is unallocated or trapped and decision processes based on these conditions
(Reiser col. 2, ll. 62-65; col. 4, ll. 15-24 (see Table); col. 8, ll. 17-19), and
Agarwal is relied upon (Agarwal pp. 122, 123) as teaching implementing the
recited functionality using microcode. Ans. 44.
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Appellants are again arguing the references separately, which we do
not find to be persuasive of Examiner error under § 103. See In re
Merck, 800 F.2d at 1097. Accordingly, Appellants have not provided
sufficient evidence or argument to persuade us of any reversible error in the
Examiner’s reading of the contested limitations on the cited prior art.
Therefore, we sustain the Examiner’s obviousness rejection of dependent
claim 3. As Appellants have not provided separate, substantive arguments
with respect to dependent claims 10 and 17 (App. Br. 18-20), rejected on the
same basis as claim 3, we similarly sustain the Examiner’s rejection of these
claims under 35 U.S.C. § 103(a).
4. Unpatentability Rejection of Claims 4, 5, 11, 12, 18, and 19
Issue 4
Appellants argue (App. Br. 20-21) the Examiner’s rejection of claim 4
under 35 U.S.C. § 103(a) as being unpatentable over the combination of
Reiser and Agarwal is in error. These contentions present us with the
following issue:
Did the Examiner err in finding that the cited prior art combination
teaches or suggests the storage medium further includes “instrumented
microcode that selectively changes the memory state indicator if the memory
state indicator indicates that the memory address is allocated but
uninitialized,” as recited in dependent claim 4?
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Analysis
Appellants again contend, inter alia, “Reiser’s ‘software tool’ is not
synonymous with Appellants’ recited ‘instrumented microcode.’” App.
Br. 21. Appellants further argue:
Nowhere does Agarwal disclose or suggest that the microcode
is patched to selectively changes the memory state indicator if
the memory state indicator indicates that the memory address is
allocated but uninitialized. In this regard, Agarwal’s microcode
captures address traces, but is not aware of whether the memory
address is allocated or uninitialized. Moreover, Agarwal’s
microcode does not include decision processes based on these
conditions. Instead, such awareness and decision processes
typically occur at the operating system or application level.
Id.
In response, the Examiner denies reliance upon either Reiser or
Agarwal individually to teach the overall limitation, but instead relies upon
the combined teachings and suggestions of the prior art. In particular, the
Examiner relies upon Reiser as teaching limitations regarding awareness of
whether the memory address is allocated but uninitialized, and decision
processes based on these conditions, and Agarwal is relied upon as
providing a teaching or suggestion of implementing the recited functionality
using microcode. Appellants’ arguments are substantially the same as those
discussed, supra, with respect to independent claim 1, and the Examiner’s
related fact finding is likewise applicable to claim 4. Ans. 45.
Further, we agree with the Examiner’s detailed explanation of the
rejection of dependent claim 4, and adopt it as our own. Ans. 8-10. The
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Examiner’s detailed findings remain unrebutted by Appellants, which
merely rely upon their arguments in the Appeal Brief. See Reply Br. 16.
Accordingly, Appellants have not provided sufficient evidence or
argument to persuade us of any reversible error in the Examiner’s reading of
the contested limitations on the cited prior art. Therefore, we sustain the
Examiner’s obviousness rejection of dependent claim 4. As Appellants have
not provided separate, substantive arguments with respect to dependent
claims 5, 11, 12, 18, and 19 (App. Br. 21-25), rejected on the same basis as
claim 4, we similarly sustain the Examiner’s rejection of these claims under
35 U.S.C. § 103(a).
5. Unpatentability Rejection of Claims 6, 13, and 20
Issue 5
Appellants argue (App. Br. 25-26) the Examiner’s rejection of claim 6
under 35 U.S.C. § 103(a) as being unpatentable over the combination of
Reiser and Agarwal is in error. These contentions present us with the
following issue:
Did the Examiner err in finding that the cited prior art combination
teaches or suggests the storage medium further includes “instrumented
microcode that reserves a range of system memory for use as a state memory
in which the at least one memory state indicator is stored,” as recited in
dependent claim 6?
Analysis
Appellants again contend, inter alia, “Reiser’s ‘software tool’ is not
synonymous with Appellants’ recited ‘instrumented microcode.’” App.
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Br. 25. Appellants further argue, “nowhere does Agarwal disclose or
suggest that the microcode is patched to reserve a range of system memory
for use as a state memory in which the at least one memory state indicator is
stored [but i]nstead, Agarwal’s microcode captures address traces.” App.
Br. 26.
Appellants’ arguments are substantially the same as those discussed,
supra, with respect to independent claim 1, and the Examiner’s related fact
finding is likewise applicable to claim 6. Ans. 48, 49.
Further, we agree with the Examiner’s detailed explanation of the
rejection of dependent claim 6, as well as the Examiner’s Response to
Arguments, and adopt these findings as our own. Ans. 10, 48, and 49. The
Examiner’s detailed findings remain unrebutted by Appellants, which
merely rely upon their arguments in the Appeal Brief. See Reply Br. 16.
Accordingly, Appellants have not provided sufficient evidence or
argument to persuade us of any reversible error in the Examiner’s reading of
the contested limitations on the cited prior art. Therefore, we sustain the
Examiner’s obviousness rejection of dependent claim 6. As Appellants have
not provided separate, substantive arguments with respect to dependent
claims 13 and 20 (App. Br. 26, 27), rejected on the same basis as claim 6, we
similarly sustain the Examiner’s rejection of these claims under 35 U.S.C.
§ 103(a).
CONCLUSIONS
(1) The Examiner did not err with respect to the non-statutory
subject matter rejection of claims 15-20 under 35 U.S.C. § 101, and we
sustain the rejection.
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(2) The Examiner did not err with respect to any of the
unpatentability rejections of claims 1-20 under 35 U.S.C. § 103(a) over the
various combinations of the prior art of record, and we sustain the rejections.
DECISION
We affirm the Examiner’s decision rejecting claims 1-20.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2011).
AFFIRMED

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