Ex Parte Haukness et alDownload PDFPatent Trial and Appeal BoardDec 13, 201612990945 (P.T.A.B. Dec. 13, 2016) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/990,945 11/03/2010 Brent S. Haukness RBS2.P074US 4803 44429 7590 12/15/2016 Peninsula Patent Omim fRamhns;^ EXAMINER 203 Woodrow Ave. Santa Cruz, CA 95060 PARIKH, KALPIT ART UNIT PAPER NUMBER 2137 NOTIFICATION DATE DELIVERY MODE 12/15/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): lkreisman@peninsulaiplaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte BRENT S. HAUKNESS, IAN SHAEFFER, and GARY B. BRONNER Appeal 2015-006043 Application 12/990,945 Technology Center 2100 Before JASON V. MORGAN, JOHN F. HORVATH, and KEVIN C. TROCK, Administrative Patent Judges. HORVATH, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Appellants seek review, under 35 U.S.C. § 134(a), of the Examiner’ rejection of claims 1—75. We have jurisdiction under 35 U.S.C. § 6(b). We AFFIRM. Appeal 2015-006043 Application 12/990,945 SUMMARY OF THE INVENTION The invention is directed to programming operations for memory devices using incremental programming techniques. Spec. 11. Claim 1, reproduced below, is illustrative of the claimed subject matter: 1. A memory system comprising: a memory device including an array of non-volatile memory cells; and a memory controller having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the memory device via a command pipeline, and configured to create a plurality of independent fractional program commands in response to the program command, wherein execution of each fractional program command incrementally programs the addressed memory cells with program data. REFERENCES Prins et al. US 2009/0172257 A1 July 2, 2009 REJECTIONS Claims 1—75 stand rejected under 35 U.S.C. § 102(e) as anticipated by Prins. Final Act. 2. ISSUES AND ANALYSIS We have reviewed the Examiner’s rejection in light of Appellants’ arguments that the Examiner has erred. We disagree with Appellants’ contentions, and adopt as our own the findings and reasons set forth by the Examiner in the Final Action and the Examiner’s Answer in response to Appellants’ Appeal Brief. We highlight the following for emphasis. 2 Appeal 2015-006043 Application 12/990,945 Claims 1—75 Issue 1: Whether Prins discloses a plurality of independent fractional program commands The Examiner finds Prins discloses this limitation, recited in claim 1, by disclosing dividing a single received write command into a plurality of transfer requests, “where each transfer request may invoke a plurality of page requests, and where each page request necessitate[s] a write to a plurality of pages on separate flash memory die . . . that comprise the actual flash memory cells to which the write operation is carried out.” Ans. 2 (citing Prins 10, 85—89, Fig. 2); Final Act. 3. The Examiner further finds that “each write to a page for a given program command may reasonably be taken as a separate fractional program command as recited in the claim,” and that Prins therefore discloses “breaking up a single host write command (program command for a same group of memory cells) into a plurality of different fractional program commands (transfer request or page requests) to carry out the write to the actual flash memory cells.” Ans. 2—3. Appellants argue the Examiner erred because Prins’ disclosure “relates to a group of smaller ‘transfer requests’ that each handle a distinct portion of the overall data,” and “does not break up a single programming request for a same group of memory cells using a plurality of independent fractional program commands.” App. Br. 15—16. We are not persuaded by Appellants argument. Prins discloses that when a flash memory controller receives a read or write command, it creates a “CDBinfo” data structure that specifies the Logical Block Address (LB A) range of flash memory cells to be read from or to which data is to be written. Prins 1 85. The controller also creates up to seven Input-Output Process 3 Appeal 2015-006043 Application 12/990,945 (IOP) data structures, known as transfer requests, each of which is “designed to handle a portion of the LB A range specified by the IOP.” Id. 11 8^87. Appellants fail to persuasively distinguish “creating] a plurality of independent fractional program commands in response to [a received] program command,” as recited in claim 1, from Prins’ dividing a received read/write request into a plurality of transfer requests, each of which handles a separate address range (LB A) of the received read/write request. Issue 2: Whether Prins discloses the execution of each fractional program command incrementally programs the addressed memory cells with program data The Examiner finds Prins discloses this limitation, also recited in claim 1, by disclosing the “[ejxecution of each transfer request involves a plurality of independent page writes ... to a given addressed group of memory cells,” whereby “[t]he completion of each separate page request constitutes an incremental programming of the addressed memory cells with program data.” Ans. 4 (citing Prins Tflf 88—89, 489, 589). Appellants argue the Examiner erred because “[ejxecution of each of Prins’ ‘Transfer Requests’ involves a complete write or programming of the data to a given addressed group of memory cells,” and therefore, “sets in motion a complete conventional programming operation that does not employ fractional program commands.” App. Br. 16. We are not persuaded by Appellants’ arguments. Appellants fail to persuasively distinguish the “wherein execution of each fractional program command incrementally programs the addressed memory cells with program data” recitation of claim 1 from Prins’ dividing a received write request into 4 Appeal 2015-006043 Application 12/990,945 multiple transfer requests, and separately executing the multiple transfer requests. Appellants further argue that the claimed invention is distinguishable from Prins’ because each of Prins’ transfer requests to program individual memory cells represents a “conventional continuous sequence of PV [program/verify] cycles to the cells.” Reply Br. 6. However, because Appellants raise this argument for the first time in the Reply Brief, and make no showing of good cause why it could not have been raised in the Appeal Brief, the argument is waived. See 37 C.F.R. § 41.41(b)(2) (2014); App. Br. 13—17; Reply Br. 4—6. Accordingly, for the reasons discussed supra, we sustain the Examiner’s rejection of representative claim 1, and of claims 2—75, which are not separately argued. See 37 C.F.R. 41.37(c)(iv) (2014); App. Br. 13. DECISION The Examiner’s rejection of claims 1—75 under 35 U.S.C. § 102(e) as anticipated by Prins is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv). AFFIRMED 5 Copy with citationCopy as parenthetical citation