Ex Parte Hara

Board of Patent Appeals and Interferences

Jul 24, 2008

10247356 (B.P.A.I. Jul. 24, 2008)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
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Ex parte TAKAHITO HARA
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Appeal 2008 -1981
Application 10/247,356
Technology Center 2100
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Decided: July 24, 2008
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Before JAMES D. THOMAS, HOWARD B. BLANKENSHIP and
ST. JOHN COURTENAY III, Administrative Patent Judges.

COURTENAY, Administrative Patent Judge.

DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) from the
Examiner’s rejection of claims 1 and 3-19. Claim 2 has been cancelled.
Claims 20 and 21 stand objected to as being dependent upon a rejected base
claim. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.

Appeal 2008-1981
Application 10/247,356

THE INVENTION
The disclosed invention relates to a semiconductor memory device
and its data writing method (Spec. 1).
Independent claim 1 is illustrative:
1. A semiconductor memory device comprising:

a memory cell that stores data;

a verify circuit that verifies data stored in the memory cell responsive
to a verify start signal and that outputs a verify pass signal when a
desired result is obtained;

a data write controlling circuit that repeats a data write operation to
the memory until the verify pass signal is input thereto, and that
generates and outputs the verify start signal after each data write
operation;

a verify pass signal invalidating circuit that invalidates the verify pass
signal when a test mode is set; and

a verify operation omitting circuit, coupled to receive the verify start
signal as output by the data write controlling circuit, that provides the
verify start signal output from the data write controlling circuit to the
verify circuit responsive to the verify pass signal output by the verify
circuit, wherein the verify operation omitting circuit stops providing
the verify start signal as output to the verify circuit for the remainder
of the test mode once the verify pass signal indicates that the desired
result is obtained, so that the data write operation is repeated for the
remainder of the test mode without verification by the verify circuit.
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THE REFERENCES
The Examiner relies upon the following references as evidence in
support of the rejection:
Watanabe US 6,292,914 B1 Sep. 18, 2001
(filed Aug. 26, 1998)
Mielke US 5,237,535 Aug. 17, 1993
(filed Oct 9, 1991)
Gross US 5,200,959 Apr. 6, 1993
(filed Oct. 17, 1989)

THE REJECTIONS
1. Claims 1, 3-6, 9, 10, 13, 14, and 17 stand rejected under 35 U.S.C.
§103(a) as being unpatentable over Wantanabe in view of Mielke .

2. Claims 7, 8, 11, 12, 15, 16, 18, and 19 stand rejected under
35 U.S.C. § 103(a) as being unpatentable over Wantanabe and Mielke, in
further view of Gross.

PRINCIPLES OF LAW
“What matters is the objective reach of the claim. If the claim extends
to what is obvious, it is invalid under § 103.” KSR Int’l Co. v. Teleflex, Inc.,
127 S. Ct. 1727, 1742 (2007). To be nonobvious, an improvement must be
“more than the predictable use of prior art elements according to their
established functions.” Id. at 1740.
Appellant has the burden on appeal to the Board to demonstrate error
in the Examiner’s position. See In re Kahn, 441 F.3d 977, 985-86 (Fed. Cir.
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Application 10/247,356

2006) (“On appeal to the Board, an applicant can overcome a rejection
[under § 103] by showing insufficient evidence of prima facie obviousness
or by rebutting the prima facie case with evidence of secondary indicia of
nonobviousness.”) (quoting In re Rouffet, 149 F.3d 1350, 1355 (Fed. Cir.
1998)). Therefore, we look to Appellant’s Briefs to show error in the
proffered prima facie case.

FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
Watanabe
1. Watanabe teaches a semiconductor memory capable of verifying
stored data (see col. 2 ll. 1-8).
2. Wantanabe teaches the claimed memory cell (col. 3 ll. 44-45),
verify circuit (col. 3 l. 66 – col. 4 l. 2), data write controlling
circuit (see col. 5 ll. 39-57), and verify pass signal invalidating
circuit (col. 4 ll. 54-65), the determination of which is not disputed
by Appellant (see App. Br. 7, et seq.).

Mielke
3. Mielke teaches repair of overerased memory cells (see Abs.).
4. Mielke teaches that by setting a bit (BAD COLUMN) a signal
conditioning pulse is applied without causing every cell on the same
column to be verified again, in order to save time (col. 13, ll. 15-18).

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Application 10/247,356

ANALYSIS
Claims 1 and 3
We consider the Examiner’s rejections under 35 U.S.C. § 103(a) of
claims 1 and 3 as being unpatentable over Watanabe and Mielke. Since
Appellant’s arguments have treated these claims as a single group which
stand or fall together, we select independent claim 1 as the representative
claim for this rejection. See 37 C.F.R. § 41.37(c)(1)(vii).
Only those arguments actually made by Appellant have been
considered in this decision. Arguments which Appellant could have made
but chose not to make in the Briefs have not been considered and are
deemed to be waived. See 37 C.F.R. § 41.37(c)(1)(vii).
Appellant contends, as acknowledged by the Examiner, that Watanabe
fails to teach the element of a verify operation omitting circuit as recited in
claim 1. Appellant further contends that contrary the Examiner’s
determination, Mielke fails to cure this deficiency (see App. Br. 8, l. 17
et seq.). More specifically, Appellant contends that the Examiner has
“misconstrued” and “misapplied” the teachings of Mielke. (App. Br. 9, ll.
9-16). According to Appellant, there is no motivation to modify the system
of Watanabe to invalidate a verification operation, as taught by Mielke, such
that the limitations of claim 1 are rendered obvious (see App. Br. 12, ll.
7-21).
We disagree. Based on the record before us, it is our view that
Appellant has misunderstood or misconstrued the Examiner’s prima facie
case. We find the basis of the Examiner’s rejection does not rest upon
whether one skilled in the art would have been motivated to bodily
incorporate Mielke’s invention into Watanabe’s invention. Indeed, it is our
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Application 10/247,356

view that the skilled artisan would not have recognized that the secondary
reference is being used to improve the primary reference. Instead, in
establishing the prima facie case for the rejection, the Examiner’s basis for
combining the teachings of Mielke with Watanabe is to show that the
function of omitting the verification operation for the sake of efficiency was
well known in the art at the time of the invention, as evidenced by Mielke.
(See Ans. 6 – 7). Thus, it is our view that the modification of Watanabe by
the teaching of Mielke would have been in accordance with what the
Supreme Court considers “common sense.”
Common sense teaches, however that familiar items may have
obvious uses beyond their primary purposes, and in many cases
a person of ordinary skill will be able to fit the teachings of
multiple patents together like pieces of a puzzle.
(KSR at 1742).

Thus, Appellant’s argument does not take into account what the
collective teachings of the prior art would have suggested to one of ordinary
skill in the art and is therefore ineffective to rebut the Examiner’s prima
facie case of obviousness. In re Keller, 642 F.2d 413, 425 (CCPA 1981)
(“The test for obviousness is not whether the features of a secondary
reference may be bodily incorporated into the structure of the primary
reference; nor is it that the claimed invention must be expressly suggested in
any one or all of the references. Rather, the test is what the combined
teachings of the references would have suggested to those of ordinary skill
in the art.”). This reasoning is applicable in the present case.
As discussed above, the Examiner determined that Watanabe teaches
all of the elements of claim 1 except for omitting the verification step for the
remainder of the test mode (FF. 2). In other words, Watanabe also teaches
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Application 10/247,356

continuing the write operation while in test mode. However, the teachings
of Mielke evidence that it was known in the art to omit the verification step,
for the sake of efficiency. Thus, the Examiner’s rejection is based on the
combination of Mielke and Watanabe, and that the combined teachings of
the references teach or suggest all of the elements of claim 1.
On the other hand, Appellant’s arguments rest upon the premise that
one skilled in the art would not have been motivated to combine the
teachings of Watanabe and Mielke (App. Br., 12-14). However, for at least
the reasons discussed above, we conclude that Appellant’s argument is
ineffective to rebut the Examiner’s prima facie case of obviousness with
regards to claim 1. Because the Appellant has not shown error in the
Examiner’s prima facie case of obviousness, we sustain the Examiner’s
rejection of representative claim 1 (and dependent claim 3 that falls
therewith) as being unpatentable over Watanabe in view of Mielke.

Claim 6
We consider next the Examiner’s rejection of claim 6 as being
unpatentable over Watanabe in view of Mielke. Appellant contends that the
cited references, most notably Mielke, fail to teach the limitations of a data
write operation to a memory cell, after the verify operation omitting circuit
becomes active, is executed by applying a voltage only to a gate from among
a source, a drain and a gate of a transistor configuring the memory cell, as
recited in claim 6. More particularly, Appellant contends that the
Examiner’s reliance on Mielke does not cure the deficiencies of Watanabe
because Mielke only shows that the repair pulse is applied to the drains of
the cells (App. Br. 17).
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Application 10/247,356

We agree with the Examiner’s determination that in a common
memory configuration, as illustrated in Fig. 2 of Mielke, one skilled in the
art would have recognized that a voltage must be applied to the gates in
order to write to the corresponding cell. (Ans. 8, ll. 1-4). Appellant’s
argument that Mielke illustrates a voltage being applied to the drains is
ineffective in rebutting the Examiner’s determination that applying a voltage
to the gate of a transistor is well-known in the art. Accordingly, we sustain
the Examiner’s rejection of claim 6 as being unpatentable over Watanabe
and Mielke.

Claims 4 and 5
We consider next the Examiner’s rejections under 35 U.S.C. § 103(a)
of claims 4 and 5. Since Appellant’s arguments have treated these claims as
a single group which stand or fall together, we select independent claim 4 as
the representative claim for this rejection. See 37 C.F.R. § 41.37(c)(1)(vii).
Appellant contends that Mielke fails to cure the deficiencies of
Watanabe. More specifically, Appellant contends that Mielke fails to teach
a test mode in which application of a repair pulse to a memory cell is
repeated without verification of the memory cell (see App. Br. 18 ll. 16-20).
We note that Appellant’s arguments are similar to those made with regards
to independent claim 1, and these arguments were fully addressed supra.
Therefore, we see no error in the Examiner’s prima facie case of
obviousness regarding claim 4. Because Appellant has not shown error in
the Examiner’s prima facie case of obviousness, we sustain the Examiner’s
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rejection of representative claim 4 (and claim 5 that falls therewith) as being
unpatentable over Watanabe and Mielke for the same reasons discussed
above regarding claim 1.

Claim 17
We consider next the Examiner’s rejection of claim 17 as being
unpatentable over Watanabe and Mielke.
We note again that Appellant’s arguments regarding the non-
obviousness of claim 17 are similar to those made regarding claim 6, i.e. that
the cited references, most notably Mielke, fail to teach the limitations of
applying a voltage to only a gate from among a source, a drain and a gate of
a transistor configuring the memory cell (see App. Br. 19). We have
addressed this line of argument supra regarding claim 6.
Therefore, we see no deficiencies regarding the Examiner’s rejection
of claim 17. Because Appellant has not shown error in the Examiner’s
prima facie case, we sustain the Examiner’s rejection of claim 17 as being
unpatentable over Watanabe and Mielke for the same reasons discussed
above regarding claim 6.

Claim 9
We consider next the Examiner’s rejection of claim 9 as being
unpatentable over Watanabe and Mielke.
Appellant contends that Mielke fails to cure the deficiencies of
Watanabe. More specifically, Appellant contends that Mielke fails to teach
a test mode in which a data write operation is repetitively executed up to a
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certain number of times once a threshold voltage of a memory cell reaches a
specific value (see App. Br. 20 ll. 17-22).
We note that Appellant’s arguments are similar to those made with
regards to independent claim 1, and these arguments were fully addressed
supra. In addition, the Examiner determined that Watanabe teaches
repetitively executing the write mode until the memory cell array reaches a
given threshold voltage (see Ans. 8 ll. 8-10).
Therefore, we see no error in the Examiner’s prima facie case of
obviousness regarding claim 9. Because Appellant has not shown error in
the Examiner’s prima facie case of obviousness, we sustain the Examiner’s
rejection of claim 9 as being unpatentable over Watanabe and Mielke for the
same reasons discussed above.

Claim 10
We consider next the Examiner’s rejection of claim 10 as being
unpatentable over Watanabe and Mielke.
We note that Appellant’s arguments regarding the non-obviousness of
claim 10 are similar to those made regarding claim 6, i.e. that the cited
references, most notably Mielke, fail to teach the limitations of applying a
voltage to only a gate from among a source, a drain and a gate of a transistor
configuring the memory cell (see App. Br. 22).
Therefore, we see no deficiencies regarding the Examiner’s rejection
of claim 10. Because Appellant has not shown error in the Examiner’s
prima facie case, we sustain the Examiner’s rejection of claim 10 as being
unpatentable over Watanabe and Mielke for the same reasons discussed
above regarding claim 6.
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Claim 13
We consider next the Examiner’s rejection of claim 13 as being
unpatentable over Watanabe and Mielke.
Appellant contends that Mielke fails to cure the deficiencies of
Watanabe. More specifically, Appellant contends that Mielke fails to teach
a test mode in which a data write operation is repetitively executed up to a
certain number of times (see App. Br. 23 ll. 10-15). We note again that
Appellant’s arguments are similar to those made with regards to independent
claim 9, and these arguments were fully addressed supra.
Therefore, we see no error in the Examiner’s prima facie case of
obviousness regarding claim 9. Because Appellant has not shown error in
the Examiner’s prima facie case of obviousness, we sustain the Examiner’s
rejection of claim 13 as being unpatentable over Watanabe and Mielke for
the same reasons discussed above.

Claim 14
We consider next the Examiner’s rejection of claim 14 as being
unpatentable over Watanabe and Mielke.
We note again that Appellant’s arguments regarding the non-
obviousness of claim 14 are similar to those made regarding claim 6, i.e. that
the cited references, most notably Mielke, fail to teach the limitations of
applying a voltage to only a gate from among a source, a drain and a gate of
a transistor configuring the memory cell (see App. Br. 24).
We see no deficiencies regarding the Examiner’s rejection of claim
14, for the reasons discussed supra regarding claim 6. Because Appellant
has not shown error in the Examiner’s prima facie case, we sustain the
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Examiner’s rejection of claim 14 as being unpatentable over Watanabe and
Mielke for the same reasons discussed above regarding claim 6.

Claims 7, 8, 11, 12, 15, 16, 18, and 19
For each of claims 7, 8, 11, 12, 15, 16, 18, and 19, Appellant merely
restates the same argument regarding the Examiner’s finding that the use of
an EEPROM or a flash EEPROM would have been obvious in view of the
Gross reference. Appellant contends that Gross fails to cure the deficiencies
of Watanabe and Mielke, i.e., that Gross does not disclose or suggest
repeating a data write operation without verification. (App. Br. 25-28).
In response, we see no deficiencies with Watanabe and Mielke, as
previously discussed. On this record, we conclude that Appellant has failed
to meet Appellant’s burden of showing error in the Examiner’s prima facie
case of obviousness for claims 7, 8, 11, 12, 15, 16, 18, and 19. Accordingly,
we sustain the Examiner’s rejection of claims 7, 8, 11, 12, 15, 16, 18, and 19
as being unpatentable over Watanabe, Mielke, and Gross.

CONCLUSION OF LAW
Based on the findings of facts and analysis above, we conclude that
Appellant has not shown that the Examiner erred in rejecting claims 1 and 3-
19 under 35 U.S.C. § 103(a) for obviousness.

DECISION
The decision of the Examiner rejecting claims 1 and 3-19 is affirmed.

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Application 10/247,356

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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