Ex Parte Hampel et al

Patent Trial and Appeal Board

Oct 25, 2012

11381349 (P.T.A.B. Oct. 25, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/381,349 05/02/2006 Craig E. Hampel 2011002 / RA473.P.US 4179
78408 7590 10/25/2012
MARC P. SCHUYLER / Rambus
P.O. BOX 2535
SARATOGA, CA 95070
EXAMINER
LI, ZHUO H
ART UNIT PAPER NUMBER
2185
MAIL DATE DELIVERY MODE
10/25/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte CRAIG E. HAMPEL and FREDERICK A. WARE
____________

Appeal 2010-005060
Application 11/381,349
Technology Center 2100
____________

Before CARL W. WHITEHEAD, JR., ERIC S. FRAHM, and
ANDREW J. DILLON, Administrative Patent Judges.

DILLON, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-42. App. Br. 5.1 We have jurisdiction under 35 U.S.C.
§ 6(b).
We affirm.

1 Throughout this opinion, we refer to the Appeal Brief filed September 2,
2009; the Examiner’s Answer mailed December 7, 2009; and the Reply
Brief filed August 2, 2010.
Appeal 2010-005060
Application 11/381,349

2
STATEMENT OF THE CASE
Appellants’ invention is directed to “[m]emory systems and memory
modules that enable more efficient use of signaling resources and reduced
memory access granularity.” Spec., ¶ [0005].
Claim 1 is illustrative, with key disputed limitations emphasized:
1. A memory module comprising:
a printed circuit board substrate;
contacts disposed at an edge of the printed circuit board
substrate to enable the memory module to be electrically
coupled to counterpart contacts of a connector;
signal lines disposed on the printed circuit board
substrate and extending from the contacts to form a control path
and first and second data paths; and
a plurality of memory devices of uniform type, including
at least first and second memory devices coupled in common to
the control path and coupled respectively to the first and
second data paths, the first and second memory devices having
control circuitry to receive respective first and second memory
access commands via the control path and to effect concurrent
data transfer on the first and second data paths in response to
the first and second memory access commands.
The Examiner relies on the following as evidence of unpatentability:
Wiggers
Laine
Halbert
US 5,892,981
US 6,687,796 B1
US 6,742,098 B1
Apr., 1999
Feb. 3, 2004
May 25, 2004
Yoo
Rader
US 6,877,079 B2
US 2006/0004976 A1
Apr. 5, 2005
Jan. 5, 2006

Appeal 2010-005060
Application 11/381,349

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THE REJECTIONS
1. The Examiner rejected claims 1, 2, 4-7, 22-25, and 34-42 under
35 U.S.C. § 103(a) as unpatentable over Halbert and Rader. App. Br. 9;
Ans. 2.
2. The Examiner rejected claims 3, 8-16, and 26-32 under § 103(a)
as unpatentable over Halbert, Rader, and Yoo. App. Br. 9; Ans. 2.
3. The Examiner rejected claims 17, 18, and 33 under § 103(a) as
unpatentable over Halbert, Rader, and Laine. App. Br. 9; Ans. 2.
4. The Examiner rejected claims 19-21 under § 103(a) as
unpatentable over Halbert, Rader, and Wiggers. App. Br. 9; Ans. 2.

ISSUE
Based upon our review of the record, the arguments proffered by
Appellants and the findings of the Examiner, we address the following issue:
Under § 103, has the Examiner erred in determining that
itwould have been obvious to concurrently access a first and second
memory device within the memory banks of Halbert’s background art
device utilizing first and second memory access commands?

ANALYSIS
Examiner’s Findings and Determinations
Each of the pending claims requires, inter alia, memory devices that
are of a uniform-type, share a control path, and are concurrently accessed in
response to respective commands. The Examiner found that Halbert’s
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Application 11/381,349

4
background art device (Figure 2)2 includes two memory devices –
particularly two memory banks (D00-08, D10-18) – that are of a uniform-
type and share a control path (RADD/RCMD). Ans. 4. In view of Rader’s
Figure 2 device, which discloses accessing two dissimilar memory devices
concurrently, the Examiner determined that it would have been obvious to
concurrently access Halbert’s memory banks. Ans. 4-5. According to the
Examiner, a skilled artisan would have made this modification “to eliminate
or reduce access latency” in view of Rader’s teachings. Ans. 5.
We agree. Like the memory banks of Halbert’s background art
device, the memory devices of Rader’s Figure 2 device have a shared control
path and are accessed in response to respective commands. Halbert, col. 2,
ll. 20-50; Fig. 3 and Rader, ¶¶ [0012], [0023-24]; Fig. 4. Halbert’s memory
banks are alternatingly accessed via a shared data path (DQ). Col. 2, ll. 20-
50; Fig. 3. Rader’s memory devices are concurrently accessed via respective
data paths (D1, D2) to reduce latency. ¶¶ [0023-24]; Fig. 4.
Given the above teachings, one skilled in the art would appreciate that
memory banks/devices of a shared control path can be alternatingly or
concurrently accessed in response to respective commands; and that
concurrent access over respective data paths reduces latency. Thus, the
modification of Halbert’s background art device – to reduce latency by
concurrently accessing the memory banks via respective data paths – applies
a known technique to a known device for an expected benefit. Such
modifications are prima facie obvious. KSR Int’l Co. v. Teleflex Inc., 550
U.S. 398, 418 (2007).

2 The Examiner cites Halbert’s Figure 1. However, Halbert’s Figures 1-2
are illustrations of the same module. Col. 2, ll. 13-18.
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Application 11/381,349

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Claims 1-16 and 19-42
Appellants argue that the modification undercuts a principle operation
of Halbert’s devices, asserting the memory banks would no longer be
concurrently accessed in response to a single command as intended. Reply
Br. 5-6. The argument is not persuasive. Both before and after
modification, the memory banks of Halbert’s background art device are
individually accessed in response to respective commands (one bank is
accessed per each command). Halbert, col. 2, ll. 20-50; Fig. 3. Appellants
are referring to the memory banks of Halbert’s invention, which
concurrently accesses two memory banks per each command so as to
increase the overall data rate. See e.g., col. 3, ll. 50-51; col. 5, l. 67 – col. 6,
l. 31; Fig. 5. The Examiner’s rejection modifies Halbert’s background art
device, not Halbert’s invention.
Appellants further argue that Halbert and Rader do not suggest an
advantage of Appellants’ invention – reduced access granularity. Reply Br.
6. The argument is not persuasive. Appellants have not shown that reduced
access granularity is a required feature of the claimed invention, much less
shown that the modification of Halbert’s background art device fails to yield
such a feature as claimed.
Note also that, to establish a prima facie case of obviousness, the
Examiner need not combine the prior art teachings in view of benefits
contemplated by the applicant. See In re Beattie, 974 F.2d 1309, 1312 (Fed.
Cir. 1992). And, though the Applicants may rebut the prima facie case by
showing such benefits were unexpectedly good, that showing must be made
with factual evidence. See In re Soni, 54 F.3d 746, 750 (Fed. Cir. 1995).
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Application 11/381,349

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Appellants’ conclusory statements about reduced granularity are insufficient.
Id.
Appellants present only the above arguments for claims 1-16 and 19-
42. In light of the above, Appellants have shown no Examiner error with
respect to the rejections of these claims.

Claims 17 and 18
Appellants present a further argument for claim 17 (see below).
Claim 18 depends from claim 17 and is argued collectively therewith. Ans.
16.
Claim 17 depends from claim 1 and recites (emphasis added):
“wherein the first memory device has an identification circuit to enable
execution of memory access commands that include a first identifier value
and the second memory device has an identification circuit to enable
execution of memory access commands that include a second identifier
value, and wherein the first and second memory access commands include
the first and second identifier values, respectively.”
The Examiner cites the schedulers (420, 421) of Laine’s Figure 4 as
suggesting an addition of identification circuits, as claimed, to Halbert’s
background art device. Ans. 11-12.
Appellants argue that the schedulers are located within Laine’s
controller (400) – not the connected memory resources (401, 402) – and
therefore fail to suggest an addition of identification circuits to Halbert’s
memory banks. App. Br. 16, fn. 1.
Appellants’ argument is not persuasive. Claim 17 requires the
memory devices to merely have, not to include, the identification circuits.
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Each of Laine’s memory resources has a respective scheduler by way of
being connected to and served by that scheduler. Fig. 4. Note also that the
schedulers pass “source/destination address words” to the respective
memory resources. Col. 7, ll. 33-45; Fig. 4. Thus, the schedulers “enable
execution” of memory access commands, as claimed.

CONCLUSION
The Examiner did not err in rejecting claims 1-42 under § 103.

ORDER
The Examiner’s decision rejecting claims 1-42 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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