Ex Parte Hampel et al

Patent Trial and Appeal Board

Sep 29, 2016

11381349 (P.T.A.B. Sep. 29, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
111381,349 0510212006 Craig E. Hampel
78408 7590 09/29/2016
MARC P. SCHUYLER I Rambus
P.O. BOX 2535
SARA TOGA, CA 95070
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
2011002 I RA473.P.US 4179
EXAMINER
LI,ZHUOH
ART UNIT PAPER NUMBER
2133
MAILDATE DELIVERY MODE
09/29/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte CRAIGE. HAMPEL and FREDERICK A. WARE
Appeal2014-006273
Application 11/381,349
Technology Center 2100
Before CARL W. WHITEHEAD, JR., ERIC S. FRAHM, and
ANDREW J. DILLON, Administrative Patent Judges.
DILLON, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's
rejection of claims 1--42. App. Br. 10. 1 We have jurisdiction under 35
U.S.C. § 6(b).
We affirm.
STATEMENT OF THE CASE
Appellants' invention relates to a memory module that is selectively
operable in a rank-wide or subrank access mode where, when operated in
rank wide mode, all memory devices respond to a single command received
via a shared command path, and when operated in sub-rank access mode,
different subranks are concurrently accessible using respective, independent
1 Throughout this opinion, we refer to the Appeal Brief filed January 17,
2014; the Examiner's Answer mailed March 7, 2014; and the Reply Brief
filed May 2, 2014.
Appeal2014-006273
Application 11/381,349
memory commands received via the shared command path. See Spec. ,-r 43,
lines 15-31.
Claim 1 is illustrative, with key disputed limitations emphasized:
1. A memory module comprising:
a printed circuit board substrate;
contacts disposed at an edge of the printed circuit board
substrate to enable the memory module to be electrically
coupled to counterpart contacts of a connector;
signal lines disposed on the printed circuit board substrate and
extending from the contacts to form a control path and first and
second data paths; and
a plurality of memory devices, including at least first and
second memory devices coupled in common to the control path
and coupled respectively to the first and second data paths;
wherein at least one of the memory module and the first and
second memory devices comprises circuitry to effect concurrent
data transfer on a selective one of (a) the first and second data
paths in response to a common memory access command and
(b) the first and second paths in response to respective first and
second memory access commands.
The Examiner relies on the following as evidence of unpatentability:
Wiggers
Laine
Halbert
Horii
Yoo
Rader
US 5,892,981 Al
US 6,687,796 Bl
US 6,742,098 Bl
US 2005/0015539 Al
US 6,877 ,079 B2
US 2006/0004976 Al
2
Apr. 6, 1999
Feb.3,2004
May 25, 2004
Jan.20,2005
Apr. 5, 2005
Jan. 5,2006
Appeal2014-006273
Application 11/381,349
THE REJECTIONS
1. The Examiner rejected claims 1, 2, 4--7, 22-25, and 34--42 under
35 U.S.C. § 103(a) as unpatentable over Halbert, Rader and Horii.
Final Act. 2-7.
2. The Examiner rejected claims 3, 8-16, and 26-32 under 35 U.S.C.
§ 103(a) as unpatentable over Halbert, Rader, Horii, and Yoo.
Final Act. 7-11.
3. The Examiner rejected claims 17, 18 and 33 under 35 U.S.C.
§ 103(a) as unpatentable over Halbert, Rader, Horii, and Laine.
Final Act. 11-12.
4. The Examiner rejected claims 19-21under35 U.S.C. § 103(a) as
unpatentable over Halbert, Rader, Horii, and Wiggers. Final Act.
12-14.
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellants'
contentions (App. Br. 10-33 and Reply Br. 1-22) that the Examiner has
erred. We have also reviewed the findings and reasons set forth by the
Examiner in (1) the action from which this appeal is taken (Final Act. 2-14),
and (2) the reasons set forth by the Examiner in the Examiner's Answer in
response to Appellants' Appeal Brief (Ans. 2-14). We highlight and
amplify certain teachings and suggestions of the references as follows.
Appellants argue the Examiner erred in rejecting claims 1, 2, 4--7, 22-
25, and 34--42 under 35 U.S.C. § 103(a) as unpatentable over Halbert, Rader
and Horii by virtue of the failure of Horii to show or suggest a memory
module "wherein at least one of the memory module and the first and second
memory devices has circuitry to effect concurrent data transfer on a selective
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Application 11/381,349
one of (a) the first and second data paths in response to a common memory
access command and (b) the first and second paths in response to respective
first and second memory access commands" which Appellants assert is
either recited expressly or substantially within each independent claim.
App. Br. 15.
Appellants assert that each of three claim groupings distinguishes the
prior art in this manner. Specifically, all claims which incorporate claim 1
(claims 2-21and36-39) directly recite the language set forth above.
Appellants argue that none of the cited references "addresses the general
concept of subrank access." Id. at 16.
In response, the Examiner points out that the Horii reference was not
relied upon by the Examiner to show or suggest the features argued as
missing by the Appellants. Rather, the Examiner relies upon Horii solely for
the teaching of "supplying command code to control simultaneously writing
multiple banks in multiple chips or an interleave writing on multiple banks
of multiple chips," as well as "an interface control unit [which] receives a
single command supplied from a host system via the interface driver,
decoding the command, and gives an operation instruction to the memory
control circuit, and the memory control unit receives the instruction and
control an access to file data in the first memory chips CHPl and CHP2."
Ans. 2-3.
In reply, Appellants address the Rader and Halbert references in detail
for the first time in this Appeal in their Reply Brief. Reply Br. 3--4. We find
"[a]ny bases for asserting error, whether factual or legal, that are not raised
in the principal brief are waived." Ex parte Borden, 93 USPQ2d 1473, 1474
(BP AI 2010) (informative). See also Optivus Tech., Inc. v. Ion Beam
Appl'ns. S.A., 469 F.3d 978, 989 (Fed. Cir. 2006) ("[A]n issue not raised by
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Application 11/381,349
an appellant in its opening brief ... is waived.") (citations and quotation
marks omitted).
Here, the Examiner's findings that claims 1, 2, 4--7, 22-25, and 34--42
are unpatentable under 35 U.S.C. § 103(a) over Halbert, Rader and Horii as
set forth in the Examiner's Answer (Ans. 2-7) are identical to those in the
Final Rejection (Final Act. 2-7), from which the instant appeal was taken.
Because the findings are identical, we find nothing that would have
prompted the new argument in the Reply Brief. The Appellants could have
made the argument in the Appeal Brief. The term "Reply Brief' is exactly
that, a brief in reply to new rejections or new arguments set forth in an
Examiner's Answer. The Appellants may not present arguments in a
piecemeal fashion, holding back arguments until an examiner answers the
original brief. This basis for asserting error is waived. See 3 7 C.F .R.
§ 41.37(c)(l)(vii).
In response to the Examiner's position holding that Horii teaches
"supplying command code to control simultaneously writing multiple banks
in multiple chips or interleave writing on multiple banks of multiple chips,"
as well as "an interface control unit [which] receives a single command
supplied from a host system via an interface driver, decoding the
command, and gives an operation instruction to the memory control circuit,
and the memory control unit receives the instruction and control an access to
file data in the first memory chips CHPI and CHP2" Appellants urge error.
Reply Br. 5.
The basis for Appellants' argument is an assertion that Horii does not
show or suggest supplying command code to simultaneously control
multiple banks in multiple chips, referring to Horii Figures 9 and 10. Id.
We find Appellants' arguments unavailing. Appellants argue that
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Figure 9 of Horii teaches that Horii fails to show or suggest the simultaneous
writing to multiple banks in multiple chips. In contrast, we note that Figure
9 of Horii is entitled "Write Speed of Flash Memory Chip Having S Banks
(At the Time of Simultaneously Writing of S Banks." (Emphasis added).
Finally, with respect to this subgroup of claims, Appellants argue that
one skilled in the art would not attempt to combine Halbert with either Rader
or Horii, since Rader and Horii relate to flash memory, which typically
requires multiple programming write cycle operations, and cannot be
combined with a rank access scheme, such as taught by Halbert. Id. at 1 7.
The Examiner responds by noting that the proper test with respect to
combined references is what the combined teachings of the references would
suggest to one of ordinary skill in the art, and not whether or not the
suggested combination is possible. The Examiner asserts that one of
ordinary skill in the art would look to combine Halbert, Rader and Horii to
suggest the features of the claimed invention. Ans. 6.
Appellants point out that independent claim 22, and claims 23-33 and
40, which depend therefrom, are patentable for the reasons set forth above,
as claim 22 recites the same language set forth above, but set forth as
method steps. App. Br. 18.
Appellants separately argue claims 34 and 41 for setting forth a
"means" for accomplishing the language argued above, and claims 35 and
42 for setting forth method steps reciting substantially the same language.
Id. at 18-19.
Finally, the Examiner notes that the elements relied upon by the
Appellants in support of patentability: the use of selective rank-wide access;
concurrent, independent subrank access modes; bimodal access; and,
selective rank-wide or subrank access, are not recited in the rejected claims.
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Ans. 5.
In view of the above, we find the Examiner did not err in rejecting
claims 1, 2, 4--7, 22-25, and 34--42 as unpatentable under 35 U.S.C. § 103(a)
over Halbert, Rader and Horii.
Appellants separately argue the patentability of claims 3, 8-16, and
26-32 under 35 U.S.C. § 103(a) as unpatentable over Halbert, Rader, Horii,
and Yoo. App. Br. 21.
Specifically, Appellants argue that claim 3 recites that each subrank of
memory comprises multiple memory devices, and urges that Yoo fails to
provide any teaching relating to rank-wide or selective concurrent subrank
access. Id. at 22.
The Examiner finds that Yoo clearly discloses each subrank memory
(figures 1, 42A, and 42B) comprising multiple memory devices (figures 1,
44) and each memory device of a set being coupled to respective signal lines
of the first data path and coupled in common to the control path (col. 4, line
62 through col. 5, line 41). Ans. 8.
Regarding claim 8, Appellants argue that the recitation of internal
sampling circuitry to sample a respective chip select within each subrank is
not shown or suggested by Yoo. App. Br. 23.
The Examiner finds that Yoo clearly discloses each subrank (figures
1, 42A, and 42B) has internal sampling circuitry (figures 1, 48) to sample a
respective chip select (col. 5, line 61 through col. 6, line 14) such that one
skilled in the art would recognize the combination of Halbert, Rader, Horii
and Yoo teaching the additional features of claim 8. Ans. 8.
Appellants separately argue claims 9-12, urging that the recitation in
claim 9, from which claims 10-12 depend, requires the independent subrank
operation is obtained by causing each subrank to sample a shared command
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path at respective times after the assertion of a chip select is not shown or
suggested by Yoo. App. Br. 23-24.
The Examiner finds that
claim 9 requires the chip select line coupled in common to a
first and second memory device and a sampling circuit in each
of first and second memory device to sample signals present on
the control path at a time relative to assertion of a chip select
signal on the chip select line to receive respective command.
Note Yoo clearly teaches each C/ A buffer in each memory
device to receive signal from memory controller via control
path and to cause memory device to output read or write data on
data bus following a predetermined time interval (col. 6 lines
15-39).
Ans. 9.
With respect to claims 13-16, Appellants argue that claim 13, from
which claims 14--16 depend, requires a common chip select line shared
across subranks, and that each subrank uses a respective chip select assertion
polarity. That is, "for example, one subrank reacts to a 'high' signal on the
shared chip select line to trigger command path sampling, and another
subrank reacts to a 'low' signal on the shared chip select line to trigger
command path sampling." App. Br. 25.
The Examiner finds that
Yoo clearly teaches to assert sample enable signal at either a
first and second time in order to synchronize data, commands
and address signals transferred between modules, thereby
enhancing overall system efficiency and reliability (col. 10 line
30 through col. 11 line 34). Thus, one of ordinary skill in the art
would recognize the combination of Halbert, Rader, Horii and
Yoo teaching the additional features of claims 13-16.
Ans. 10.
Appellants argue, regarding claims 26-32, that the Examiner did not
properly address those claims, but rather merely noted their rejection "for
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the same reasons as set forth in claims 9-12." App. Br. 26. Appellants note
that these claims depend from claim 22 and that none of cited references
shows or suggests "selective rank-wide or concurrent subrank-specific
access as required by independent claim 22." Id.
Appellants also separately argue claims 27-30, which each recite that
the subrank operation is "obtained by causing each subrank to sample a
shared command path at times following the assertion of a respective chip
select." Appellants urge that the Examiner has incorrectly asserted that Yoo
teaches "a varied sampling latency by memory devices of a memory module
of a shared command bus." Id.
In response, the Examiner finds that these claims differ from claims
9-12 by the defining of enabling respective receiver circuits within first and
second memory devices to sample signals present on the control path at non-
overlapping intervals. The Examiner finds that "Yoo clearly teaches a
receiving step comprising enabling respective receiver circuits within the
first and second memory devices to sample signals present on the control
path at respective, non-overlapping intervals (col. 5 line 61 through col. 6
line 14)." Ans. 10.
Further, Appellants individually and specifically argue claims 28, 29,
and 30, asserting that the cited references fail to show or suggest: the chip
select signals arrive via independent chip select lines; the chip select signals
arrive via a common chip select line, with each subrank using a different
chip select assertion polarity; and, the chip select polarity used by the first
memory device is defined by programming a configuration register in the
first memory device, respectively. App. Br. 27.
The Examiner cites Yoo, at column 5, lines 13-28, which shows
"convey[ing] the first and second chip select signals between the first and
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second memory modules via independent chip select lines (col. 5 lines 13-
28, utilizing independent bus line to convey control signal between first and
second memory modules)." Ans. 11.
The final group of claims addressed under the second ground of
rejection, claims 31 and 32, are argued by Appellants as patentably distinct
from the references cited by the Examiner by virtue of the recitation of: "a
common chip select signal across subranks (i.e., for both of the first and
second memory devices) and that sampling of command path signals is
responsive to assertion of the common chip select but using respective
sampling latencies by each subrank;" and, a "sampling latency is effectuated
in the second memory device by a programmable latency, expressed as a
number of clock cycles by which sampling of the command path is delayed
following assertion of the common chip select." Appellants argue that Yoo
fails to show or suggest these features. Appeal Br. 28.
The Examiner finds
r oo clearly teaches to aerny sampling wnnm the second
memory module be a number of clock cycles indicated by a
sample-latency value stored in a configuration register (col. 6
line 62 through col. 7 line 20). As demonstrated above, Yoo
supports command path sampling latency, and chipselect
architecture as recited by Applicant's claims. [Thus], Yoo
teaches chip selects or chip select architecture.
Ans. 11.
Appellants address this ground of rejection in their Reply Brief;
however, we find the arguments at Reply Brief 12-17 constitute reiteration
of the Appeal Brief arguments, or mere attorney argument and are not
considered persuasive.
Turning to the third ground of rejection, Appellants argue the
Examiner erred in rejecting claims 17, 18, and 23 under 35 U.S.C. § 103(a)
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Application 11/381,349
as unpatentable over Halbert, Rader, Horii, and Laine. Specifically,
Appellants argue that the cited references fail to show or suggest the recited
circuitry whereby
each memory device can be selectively caused to respond in
response to a common command sent via a shared command
bus, with respective data shared over respective data paths (i.e.,
rank-wide response in response to a common address) or, using
subrank specific identifier codes, a command and address can
be transmitted to all devices but also be directed to a specific
subrank (memory device) using such code as an additional part
of a command.
Appellants also urge that the Examiner's position that
Laine teaches a scheduler coupled to each memory ( 401 and
402, figure 4) for enabling execution of commands that
includes respective identifier such that each schedule includes a
register to store respective identifier in response to the
command from CPU (403, figure 4) in order to provide
flexibility in parallel transfer
is completely unsupported. Appeal Br. 30.
In response, the Examiner finds that the schedulers disclosed by Laine
in Figure 4 are described as providing an address for each transaction
performed on a clock cycle (col. 7, lines 23-27) which the Examiner finds
suggests an identifier code, as claimed. Ans. 11-12.
In reply, Appellants assert that Laine fails to show or suggest memory
device ID codes. Reply Br. 18.
We find the Examiner's position persuasive. The use of addresses by
the schedulers of Laine is highly suggestive of ID codes. We therefore find
that the Examiner did not err in rejecting claims 17, 18, and 23 under 35
U.S.C. § 103(a) as unpatentable over Halbert, Rader, Horii, and Laine.
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Finally, with respect to the fourth ground of rejection, Appellants
argue that the Examiner erred in rejecting claims 19-21under35 U.S.C.
§ 103(a) as unpatentable over Halbert, Rader, Horii, and Wiggers.
Appellants argue that Wiggers discloses many memory devices but fails to
disclose any teaching of subrank access or the use of chip select signals.
Further, Appellants urge that Wiggers does not suggest the four independent
memory access commands that are transmitted over a shared command path
and responsive concurrent data transfer. Appeal Br. 31-32.
In response to Appellants' argument that Wiggers fails to show
subrank access or chip select signals, the Examiner finds those features are
disclosed in Halbert, Rader and Horii, and that Wiggers is merely cited for
the feature of first, second, third and fourth memory devices, which are
clearly shown in Figure 3 of Wiggers. Ans. 12-13.
In reply, Appellants argue that the Examiner's reliance upon Halbert,
Rader and Horii is not well founded, for the reasons set forth above. Reply
Br. 20-21.
For the reasons we set forth above we do not find the Appellants'
position to be persuasive.
ORDER
The Examiner's decision rejecting claims 1--42 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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