Ex Parte Hamlin et al

Patent Trial and Appeal Board

Jan 14, 2013

10768588 (P.T.A.B. Jan. 14, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte CHRISTOPHER L. HAMLIN, JAMES S. KOFORD,
and DOUGLAS B. BOYLE
____________________

Appeal 2010-005936
Application 10/768,588
Technology Center 2100
____________________

Before KALYAN K. DESHPANDE, TREVOR M. JEFFERSON, and
LARRY J. HUME, Administrative Patent Judges.

DESHPANDE, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-005936
Application 10/768,588

2
STATEMENT OF CASE
1

The Appellants seek review under 35 U.S.C. § 134(a) of a final
rejection of claims 1-7 and 15-21, the only claims pending in the application
on appeal. We have jurisdiction over the appeal pursuant to 35 U.S.C.
§ 6(b).
We AFFIRM.

The Appellants invented a method and apparatus for mapping
platform-based design to multiple foundry processes.
An understanding of the invention can be derived from a reading of
exemplary claim 1, which is reproduced below [some paragraphing added]:
1. A method for mapping an integrated circuit design to
multiple foundry processes, comprising steps of:
a) checking availability of features of an integrated circuit
design in a first target foundry process, said design including
base wafer layers and metal stack layers;
b) selecting a base wafer/metal stack interface layer for said
design;
c) creating blocks compatible with:
a first base wafer process of said target foundry process,
a second base wafer process of a second foundry process,
and
a metal stack layer common to the first base wafer
process and the second base wafer process;
d) creating a physical design library for said design; and
e) creating a logic design and timing library for said design.

1
Our decision will make reference to the Appellants’ Appeal Brief (“App.
Br.,” filed October 8, 2010), Reply Brief (“Reply Br.,” filed February 26,
2010), Examiner’s Answer (“Ans.,” mailed January 6, 2010), and Final
Rejection (“Final Rej.,” mailed March 19, 2009).
Appeal 2010-005936
Application 10/768,588

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REFERENCES
The Examiner relies on the following prior art:
Lee
Gamal
US 5,500,805
US 5,754,826
Mar. 19, 1996
May 19, 1998

Youcef Bourai and C.-J. Richard Shi, “Layout Compaction for Yield
Optimization via Critical Area Minimization,” (Electrical Engineering
Department, University of Washington, 2000).

REJECTIONS
2

Claims 1-7 and 15-21 stand rejected under 35 U.S.C. § 112, second
paragraph, as being indefinite. Ans. 4.
Claims 1-5, 7, 15-19, and 21-23 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Gamal and Lee. Ans. 6-9.
Claims 6 and 20 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Gamal, Lee, and Bourai. Ans. 9-10.

ISSUES
The issue of whether the Examiner erred in rejecting claims 1-7 and
15-21 under 35 U.S.C. § 112, second paragraph, as being indefinite turns on
whether a person with ordinary skill in the art would have understood what
was being claimed with respect to the limitation “checking availability of
features of an integrated circuit design in a first target foundry process, said
design including base wafer layers and metal stack layers.”

2
The Examiner’s rejection the claims under 35 U.S.C § 112, first paragraph,
for failing to comply with the enablement requirement has been withdrawn.
Ans. 2.
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Application 10/768,588

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The issue of whether the Examiner erred in rejecting claims 1-5, 7,
15-19, and 21-23 under 35 U.S.C. § 103(a) as being unpatentable over
Gamal and Lee turns on whether the combination of Gamal and Lee teaches
or suggests limitations (b) and (c) of independent claims 1 and 15, whether
the Examiner’s rejection is based on impermissible hindsight reconstruction,
and whether there is a motivation to combine the cited prior art.
The issue of whether the Examiner erred in rejecting claims 6 and 20
under 35 U.S.C. § 103(a) as being unpatentable over Gamal, Lee, and Bourai
turns on whether Appellants’ arguments in support of independent claims 1
and 15 are found to be persuasive.

ANALYSIS
Claims 1-7 and 15-21 rejected under 35 U.S.C. § 112, second paragraph, as
being indefinite
The Examiner found that limitation (a) of claims 1 and 15 recites
“checking availability of features of an integrated circuit design in a first
target foundry process, said design including base wafer layers and metal
stack layers” and this limitation renders claims 1-7 and 15-21 indefinite.
Ans. 4.
We disagree. The test for definiteness under 35 U.S.C. § 112, second
paragraph, is whether “those skilled in the art would understand what is
claimed when the claim is read in light of the specification.” Orthokinetics,
Inc. v. Safety Travel Chairs, Inc., 806 F.2d 1565, 1576 (Fed. Cir. 1986)
(citations omitted). While the Examiner finds that “what [A]ppellant[s]
considers as integrated circuit components is not pointed out in the
specification” (Ans. 4), the Examiner has not provided any evidence or
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rationale to illustrate which elements in this limitation a person with
ordinary skill in the art would not understand. Accordingly, we do not
sustain the Examiner’s rejection of claims 1-7 and 15-21 under 35 U.S.C.
§ 112, second paragraph as being indefinite.

Claims 1-5, 7, 15-19, and 21-23 rejected under 35 U.S.C. §103(a) as being
unpatentable over Gamal and Lee
We have reviewed the Examiner’s rejections in light of Appellants’
contentions that the Examiner has erred.
We disagree with Appellants’ conclusions. We adopt as our own
(1) the findings and reasons set forth by the Examiner in the action from
which this appeal is taken and (2) the reasons set forth by the Examiner in
the Examiner’s Answer in response to Appellants’ Appeal Brief. We concur
with the conclusion reached by the Examiner. We highlight the following
arguments for emphasis.
Appellants contend that the combination of Gamal and Lee fails to
teach or suggest “selecting a base wafer/metal stack interface layer for said
design” and “creating blocks compatible with: a first base wafer process of
said target foundry process, a second base wafer process of a second foundry
process, and a metal stack layer common to the first base wafer process and
the second base wafer process,” as recited in limitations (b) and (c) of
independent claims 1 and 15. App. Br. 20-26 and Reply Br. 8-9. However,
we are unpersuaded by Appellants’ arguments.
With respect to limitation (b), the Examiner found that Gamal
describes the design of an integrated circuit (IC) using design rules, in a
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generic library, and a software program hierarchically transforms the generic
layout to a specific layout. Ans. 11 (citing Gamal 3:45-67 and 4:37-43).
The Examiner further found that Gamal describes that the conversion from
generic layout to specific layout requires selecting all base and metal mask
layers. Ans. 11-12 (citing Gamal 8:6-8). While Appellants have
acknowledged this disclosure of Gamal (App. Br. 20-22), Appellants have
not provided any evidence or rationale to distinguish the requirements of
independent claims 1 and 15 from this disclosure cited by the Examiner.
Absent any evidence or rationale from Appellants, we do not find this
argument to be persuasive.
With respect to limitation (c) the Examiner found that Lee discloses a
metal stack layer common to both first and second base wafer process as
show by M1 and M2, where the most restrictive pitch is the one used as the
common pitch thereby making the metal stack layer common to first and
second base wafer process. Ans. 13 (citing Lee Fig. 2 and 7:13-44). As
noted by the Examiner (Ans. 13), Appellants acknowledge this disclosure in
Lee but do not set forth an evidence or rationale to distinguish the claimed
invention from this disclosure. As such, we do not find Appellants’
argument to be persuasive.
Appellants further contend that there is no teaching to
modify/combine Gamal and Lee and the Examiner’s rejection is based on
impermissible hindsight reconstruction. App. Br. 26-29. We disagree with
Appellants. We find that the Examiner has fully responded to these
arguments. Ans. 14-16. Accordingly, we adopt the Examiner’s findings and
conclusions as our own.

Appeal 2010-005936
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Claims 6 and 20 rejected under 35 U.S.C. § 103(a) as being unpatentable
over Gamal, Lee, and Bourai
Appellants do not present separate arguments for the patentability of
claims 6 and 20 and therefore we find that the Examiner did not err in
rejecting these claims for the same reasons discussed supra with respect to
independent claims 1 and 15.

CONCLUSIONS
The Examiner erred in rejecting claims 1-7 and 15-21 under 35 U.S.C. §
112, second paragraph, as being indefinite.
The Examiner did not err in rejecting claims 1-5, 7, 15-19, and 21-23
under 35 U.S.C. §103(a) as being unpatentable over Gamal and Lee.
The Examiner did not err in rejecting claims 6 and 20 under 35 U.S.C.
§103(a) as being unpatentable over Gamal, Lee, and Bourai.

DECISION
To summarize, our decision is as follows.
 The rejection of claims 1-7 and 15-21 under 35 U.S.C. § 112, second
paragraph, as being indefinite is not sustained.
 The rejection of claims 1-5, 7, 15-19, and 21-23 under 35 U.S.C.
§ 103(a) as being unpatentable over Gamal and Lee is sustained.
 The rejection of claims 6 and 20 under 35 U.S.C. § 103(a) as being
unpatentable over Gamal, Lee, and Bourai is sustained.

Appeal 2010-005936
Application 10/768,588

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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2011).

AFFIRMED

ELD