Ex Parte Hamilton et al

Patent Trial and Appeal Board

Aug 23, 2016

13494382 (P.T.A.B. Aug. 23, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/494,382 06/12/2012
60501 7590 08/25/2016
LENOVO COMPANY (LENOVO-KLS)
c/o Kennedy Lenart Spraggins LLP
8601 Ranch Road 2222
Ste. 1-225
AUSTIN, TX 78730
FIRST NAMED INVENTOR
Jeffrey R. Hamilton
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
XRPS920100092US2 7228
EXAMINER
KROFCHECK, MICHAEL C
ART UNIT PAPER NUMBER
2138
NOTIFICATION DATE DELIVERY MODE
08/25/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
office@klspatents.com
kate@klspatents.com
hanna@klspatents.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JEFFREY R. HAMIL TON, MELBA I. LOPEZ,
ROSS L. MICKENS, and MARKESHA F. PARKER
Appeal2015-002285
Application 13/494,382
Technology Center 2100
Before JOSEPH L. DIXON, JOHN P. PINKERTON, and
NATHAN A. ENGELS, Administrative Patent Judges.
DIXON, Administrative Patent Judge.
DECISION ON APPEAL
Appeal2015-002285
Application 13/494,382
STATE~vfENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from a rejection of claims
1-3 and 7-9. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
The claims are directed to a backup memory administration using an
active memory device and a backup memory device. Claim 1, reproduced
below, is illustrative of the claimed subject matter:
1. A method of backup memory administration comprising:
storing in an active memory device, by a memory backup
controller, blocks of computer data received from random access
memory, wherein the active memory device comprises a first
flash memory and is communicably coupled to the memory
backup controller via a memory device adapter by a first
connector connecting the active memory device to the memory
device adapter;
recording in a change log, by the memory backup
controller, identifications of each block of computer data that is
stored in the active memory device;
detecting, by the memory backup controller, a backup
trigger event; and
responsive to the detecting of the backup trigger event:
copying, by the memory backup controller, from the active
memory device, to a backup memory device, the blocks of data
identified in the change log, wherein the backup memory device
comprises a second flash memory and is communicably coupled
to the memory backup controller via the memory device adapter
by a second connector connecting the backup memory device to
the memory device adapter, wherein the first connector and the
second connector are independent of each other; and
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clearing, by the memory backup controller, the change log,
wherein the backup trigger event is triggered in response to one
of a change in a power state of a processor and a change in the
power state of the memory backup controller.
REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Prabhu US 2003/0056062 Al Mar. 20, 2003
Innan et al. US 2003/0088592 Al May 8, 2003
Kawamura US 2005/0240637 Al Oct. 27, 2005
Shin et al. US 2006/0069931 Al Mar. 30, 2006
Okada et al. US 2007/0266215 Al Nov. 15, 2007
Harari et al. US 7,362,618 B2 Apr. 22, 2008
Sela et al. US 2010/0030982 Al Feb.4,2010
REJECTIONS
The Examiner made the following rejections:
Claim 7 is rejected under 35 U.S.C. l 12(a) or 35 U.S.C. 112 (pre-
AIA), first paragraph, as failing to comply with the written description
requirement. The claim(s) contains subject matter which was not described
in the specification in such a way as to reasonably convey to one skilled in
the relevant art that the inventor or a joint inventor, or for pre-AIA the
inventor( s ), at the time the application was filed, had possession of the
claimed invention. 1
1 The Examiner has withdrawn the rejection of claim 1 [sic, 7] under 35
U.S.C. § 112, first paragraph. (Ans. 3).
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Claims 1 and 7 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Kawamura, Prabhu, Sela, and Shin.
Claims 2 and 3 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Kawamura, Prabhu, Sela and Shin as applied to claim 1
above, and further in view of Harari and Okada.
Claims 8 and 9 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Kawamura, Prabhu, Sela as applied to claim 1 above, and
further in view of lnnan.
ANALYSIS
35 U.S.C. § 103(a)
With respect to claims 1 and 7, Appellants present arguments to the
claims as a group. (App. Br. 6). As a result, we select independent claim 1
as the representative claim for the group and will address Appellants'
arguments thereto.
With respect to representative independent claim 1, Appellants
contend no combination of the cited references can be used to establish a
prima facie case of obviousness against the claims because any combination
of cited references does not teach or suggest every element and limitation
recited in the independent claims. (App. Br. 6). Appellants contend that the
cited paragraphs of the Kawamura reference do not disclose the claimed
"recording in a change log, by the memory backup controller, identifications
of each block of computer data that is stored in the active memory device."
(App. Br. 6-7). Appellants further contend that in the Kawamura reference,
the update bitmap management table includes bit information indicating
changes in the backup target DB region rather than the change log records
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"identifications of each block of computer data that is stored in the active
memory device." (App. Br. 7).
The Examiner maintains:
Looking at paragraphs 29-31 of Kawamura, the DB buffer
stores DB blocks from the storage unit and upon receipt of a
request from the checkpoint processing unit, transfers the
contents of the DB buffer on to the backup target DB region
(claimed active memory device). Then the bitmap processing
unit updates an update bitmap management table (claimed
change log) which stores information indicating that the data has
been updated in a storage device. A bitmap is a map that stores
1 bit to represent a[ n] particular memory location. This bitmap
tracks the updating of data in the backup target DB region
volume, so the bitmap would indicate each location in the backup
target DB region volume that contains updated information. The
backing up or copying of the data in the backup target DB region
to differential backup volume (113) occurs using that update bit
information in the bitmap management table. Thus Kawamura
teaches "recording in a change log, by the memory backup
controller, identification of each block of computer data that is
stored in the active memory device," as presented in the claims.
(Ans. 4--5). The Examiner further maintains:
(2), the appellant does not explicitly explain how the term
active causes the claimed active memory device to be different
from the backup target DB region (111) of Kawamura. The term
"active" is not specially defined within the current specification
and it does not hold a special meaning in the computer memory
art. Any memory device that is in use and not turned off, can be
an "active memory device." Even though the backup target DB
region (111) is a backup device, as opposed to a non-backup
storage device (fig. 1, paragraph 29-31 ), it still reads on an active
memory device because the backup target DB region (111)
receives and stores the DB blocks that have been updated from
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the DB buffer. The backup target DB region (111) is actively
used in Kawamura.
(Ans. 5).
We find the Examiner's explanation and line of reasoning to be
reasonable. The Examiner's Answer further explains the application of the
prior art teachings of the Kawamura reference, and Appellants have not filed
a reply brief to show error in the Examiner's clarification of the rejection in
the Answer.
Appellants further contend:
The Office Action takes the position that Sela at paragraphs
[0013] and [0087]-[0092] disclose "wherein the backup memory
device comprises a second flash memory and is communicably
coupled to the memory backup controller via the memory device
adapter by a second connector connecting the backup memory
device to the memory device adapter, wherein the first connector
and the second connector are independent of each other." We
note, in response, that paragraphs [0088]-[0089] actually
disclose:
[0088] Third party 310 is operatively connected, via data
network (e.g., the Internet) 390, to a host device system
305. Host device system 305 includes one host device 320
that has associated with it two card readers: card reader
330 and card reader 340. Card readers 330 and 340 are
external to host device 320. By way of example, card
reader 330 accommodates source S SD 350 and card reader
340 accommodates destination SSD 360.
[0089] After satisfying eligibility prerequisites that are
specified above, third party 310 establishes a virtual secure
channel between source SSD 350 and destination SSD
360, by establishing a first secure channel with source
SSD 350 and a second secure channel with destination
SSD 360. The first secure channel is established over
communication lines 355 and 380, and via data network
390, and the second secure channel is established over
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communication lines 365 and 380, and via data network
390.
That is, Sela merely discloses that two card readers are connected
to the host device 320 over communication lines 355 and 365. It
is unclear what the Examiner contends discloses the device
adapter, or the first and second connectors, but Sela merely
discloses that two card readers are connected to a host device by
two communication lines. Accordingly, nothing in the cited
portion of Sela, or the remaining cited art, discloses any memory
device adapter as claimed.
(App. Br. 8).
The Examiner further explains the application of the prior art
teachings of the Sela reference in the prior art combination.
The examiner stated on pages 5-6 of the final office action
mailed on 3/20/2014 that Sela's host device (fig. 3, item 320) is
the claimed memory device adapter, the third party (item 310) is
the claimed memory backup controller, and that communication
lines 355 and 365 are the connector. The claim language states,
"wherein the backup memory device comprises a second flash
memory and is communicably coupled to the memory backup
controller via the memory device adapter by a second connector
connecting the backup memory device to the memory device
adapter, wherein the first connector and the second connector are
independent of each other."
Referring to figure 3 of Sela and paragraphs 87-92,
destination SSD (360) is the claimed backup memory device
including a second flash memory. As stated above, the third party
(310) is the claimed memory backup controller since it creates
the secure channel between the card readers (paragraph 89) and
then controls the backup operations (paragraphs 90-92). "After
third party 310 reads the digital data from source SSD 350 third
party logs on ... into destination SSD 360 ... third party writes the
data it read from source SSD 350 into destination SSD 360."
Looking at figure 3, one can clearly see that destination SSD is
communicably coupled to third party through the card reader
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(340), host device (320), and network (390). Host device (320)
is analogous to the claimed memory device adapter because it
communicably coupling both the source SSD and the destination
SSD to the third party (paragraph[ s] 88, 91 ), satisfying the
requirements of the claims. It serves as the intermediate,
adapting communication between the third part and the storage.
Card reader (340) and communication line (365) makeup the
second connector since they connect the destination SSD
(backup memory device) to the host device (memory device
adapter). Furthermore, a card reader inherently contains a
physical connector that physically connects the pins of the SSD
to the card reader circuitry in order for the SSD to operate. The
claimed first connector is the card reader (330) and the
communication line (355) which is analogous to the claimed
second connector.
Additionally referring to figure 3, one can clearly see that
items 330 and 355 (the first connector) and items 365 and 340
(the second connector) are separate from each other and therefore
independent of each other.
(Ans. 6-7).
We find the Examiner's explanation and line of reasoning to be
reasonable. The Examiner's Answer further explains the application of the
prior art teachings of the Sela reference, and Appellants have not filed a
Reply Brief to show error in the Examiner's clarification of the rejection in
the Answer. As a result, Appellants have not shown error in the Examiner's
conclusion of obviousness of independent claim 1, and we sustain the
rejection of representative independent claim 1.
Appellants have not presented separate arguments for patentability of
claims 2, 3, 8, and 9. Consequently, we group these claims as falling with
representative independent claim 1.
CONCLUSIONS
The Examiner did not err in rejecting claims 1-3 and 7-9 under 35
U.S.C. § 103(a).
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DECISION
For the above reasons, we sustain the Examiner's obviousness
rejection of claims 1-3 and 7-9.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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