Ex Parte Hady

Board of Patent Appeals and Interferences

Sep 10, 2007

10185476 (B.P.A.I. Sep. 10, 2007)

The opinion in support of the decision being entered today
is not binding precedent of the Board.

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
_____________

Ex parte FRANK T. HADY
_____________

Appeal 2007-1756
Application 10/185,476
Technology Center 2100
______________

Decided: September 10, 2007
_______________

Before JAMES D, THOMAS, JOSEPH F. RUGGIERO,
and ROBERT E. NAPPI, Administrative Patent Judges.

NAPPI, Administrative Patent Judge.

DECISION ON APPEAL

This is a decision on appeal under 35 U.S.C. § 6(b) (2002) of the final
rejection of claims 1 through 10, 19 through 23, and 35 through 46. For the
reasons stated infra, we affirm in part the Examiner’s rejection of these
claims.

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INVENTION

The invention is directed to a system which includes a network
processor and a host processor. The system is implemented such that writes
by the network processor to memory associated with the network processor
also write to the memory associated with the host processor. See page 8 of
Appellant’s Specification. Claims 1 and 35 are representative of the
invention and reproduced below:
1. A method comprising:
processing a network message in a network processor; and
writing data associated with said message to a memory
associated with the network processor and to a memory associated
with a host processor coupled to said network processor using a single
network processor instruction to write to both memories.

35. A general purpose processor-based system comprising:
a general purpose processor;
a host bus coupled to said general purpose processor; and
a storage coupled to said general purpose processor to be
written with data associated with a network message by a network
processor and by said general purpose processor, said network
processor coupled to said general purpose processor-based system by
the host bus.

REFERENCES

The references relied upon by the Examiner are:

Bass US 6,675,163 B1 Jan. 6, 2004
(filed Apr. 6, 2000)

Kale US 6,754,735 B2 Jun. 22, 2004
(filed Dec. 21, 2001)

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REJECTIONS AT ISSUE
Claims 1 through 4, 7 through 10, 19 through 23, 35, 36, 38 through
40, and 43 through 461 stand rejected under 35 U.S.C. § 102 (e) as being
anticipated by Kale. The Examiner’s rejection is set forth on pages 4
through 8 of the Answer. Claims 5, 6, 37, 41, and 422 stand rejected under
35 U.S.C. § 103 (a) as being unpatentable over Kale in view of Bass. The
Examiner’s rejection is set forth on pages 4 through 13 of the Answer.
Throughout the opinion, we make reference to the Brief (received
May 12, 2006), the Reply Brief (received August 31, 2006) and the Answer
(mailed July 27, 2006) for the respective details thereof.

ISSUES
Appellant contends that the Examiner’s rejection of claims 1 through
4, 7 through 10, 19 through 23, 35, 36, 38 through 40 and 43 through 46
under 35 U.S.C. § 102 (e) is in error. Appellant asserts that Kale does not
teach using the same instruction to write to both a memory associated with
the network processor and the memory associated with the host processor.
(Br. 10). With respect to claim 35, Appellant contends that “The suggestion
[in Kale] that various elements described can be different portions of the

1 We note that the statement of the rejection includes claims 37, 41 and 42
and does not include claim 36. However, the rationale supporting the
rejection discusses claim 36 but does not discuss claims 37, 41 and 42.
Accordingly, we consider claim 36 to be included in the rejection but not
claims 37, 41 and 42.
2 We note that the statement of the rejection does not include claims 41 and
42. However, the rationale supporting the rejection includes claims 41 and
42. Accordingly, we consider claims 41 and 42 to be included in the
rejection.
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same network processor memory does not teach that they can be written to
both by the host processor and the network processor.” (Br. 11).
In response the Examiner states:
Kale discloses a method or “'technique' that provides improved data
transfer between a host processor, and one or more associated
'processing devices' (e.g. network processors) known as a Single
Descriptor Scatter Gather technique: The technique allows a 'single
descriptor' to be used to control the transfer of data to or from
multiple non-contiguous memory locations [col 3, lines 4-19]. Kale
discloses Steps A-E to accomplish the said 'technique' used to transfer
the data, as illustrated in Figure 3 [col 4, lines 19-30].

(Answer 15). Additionally, the Examiner finds that the limitation of using a
single network processor instruction to write to both memories is taught by
Kale‘s teaching that the host processor updates its own copy of the
descriptor head pointer in host descriptor table and also writes this value in
to the set of pointers of the network processor. (Answer 15-16). With
regard to claim 35, the Examiner finds that Kale teaches a storage that can
be written to by both a general purpose processor and a network processor.
Thus the contentions of Appellant and the Examiner present us with
two issues.
The first issue is whether Kale teaches using the same instruction to
write to both a memory associated with the network processor and the
memory associated with the host processor as recited in independent claims
1, 19 and 40. This issue does not apply to independent claim 35 as claim 35
does not recite a single instruction writing to two memories.
The second issue is whether Kale teaches a storage coupled to a
general purpose processor that can be written to by both a network processor
and a general purpose processor. This issue does not apply to independent
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claims 1, 19 and 40, as these claims do not recite a limitation directed to one
memory being written to by two processors.

FINDINGS OF FACT
1) Kale teaches a system to control the transfer of information
from scattered (non-contiguous) memory locations.
(Abstract).
2) Kale’s system makes use of descriptors which are associated
with a region of a host memory that includes the address for
each of the non-contiguous memory locations of the
network processor to be written to or from. (Col. 5, ll. 5-
24).
3) These descriptors are stored in a host descriptor table (item
114). The table and descriptors are generated by the host
computer system. (Col. 4, ll. 32-48).
4) The host descriptor table is stored in the host computer
memory. (Col. 3, ll. 48-54).
5) The host also generates a host descriptor head pointer and
tail pointer which define the beginning and end of the
descriptor table. These pointers are stored in two memories,
one associated with the host processor and the other
associated with the network processor. (Col. 4, ll. 49-57).
6) The network processor uses the pointers to find and read the
appropriate descriptor from the host descriptor table (in host
memory). Based upon the descriptor the network processor
performs the data transfer. (Col. 5, ll. 42-53).
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7) After the data transfer is complete the network processor
updates the descriptor tail pointer3 in the network processor
and writes to the set of network tail pointers in the host
processor’s memory. The network processor continues data
transfers until the tail and head pointers match. (Col. 5, l.
64- Col. 6, l. 15).

ANALYSIS
On the first issue, we disagree with the Examiner’s finding that Kale
teaches using the same instruction to write to both a memory associated with
the network processor and the memory associated with the host processor.
Independent claim 1 recites: “writing data associated with said message to a
memory associated with the network processor and to a memory associated
with a host processor coupled to said network processor using a single
network processor instruction to write to both memories.” Independent
claims 19 and 40 recite similar limitations. From the Examiner’s statements
on pages 14 and 15 of the Answer, it is unclear as to whether the Examiner
is relying upon Kale’s teaching of using a descriptor to transfer data to or
from host memory to meet the claimed single instruction writing to two
memories. As discussed in our findings of fact above, we find that Kale
teaches that a descriptor can be used to write to dis-continuous memory
locations. Facts 2 and 6. However, we do not find that Kale teaches that the
same descriptor performs a write to both the host processor memory and the

3 We believe the reference contains a typographical error and should read
updates the descriptor head pointer as the system performs data transfers
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network processor memory. Further, we do not find that Kale’s teaching of
the descriptor head and tail pointers being updated in the network processor
memory and written to the host processor memory necessarily teaches that
the value is written to both memories with one instruction. We find no
suggestion in Kale that this updating and writing be performed with one
instruction and, given that they are referred to as two types of operations
(updating and writing), we find no suggestion or indication that they
inherently are performed by one instruction. Thus, Appellant’s contention
has persuaded us of error in the Examiner’s rejection of independent claims
1, 19 and 40.
On the second issue, we disagree with Appellant’s assertion that Kale
does not teach one storage that can be written to by two processors.
Independent claim 35 recites “a storage coupled to said general purpose
processor to be written with data associated with a network message by a
network processor and by said general purpose processor, said network
processor coupled to said general purpose processor-based system by the
host bus.” Thus the scope of claim 35 includes that there is one storage that
can be written to by both the network processor and the host processor. As
discussed in our findings of fact, Kale teaches that the host processor
memory contains a list of host descriptor pointers. (Fact 5). This memory is
written to by the host processor which makes up descriptor pointers. (Fact
5). Kale also teaches that the network processor writes to the host memory
descriptor pointers as it is executing the descriptors. (Fact 7). Thus, we find

based upon the descriptor identified by the descriptor head portion and not
the tail portion.
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ample evidence to support the Examiner’s finding that Kale teaches a
storage that is written to by both the host and network processors.
Appellant has presented no arguments directed to the Examiner’s
rejection of dependent claims 5, 6, 37, 41, and 42 under 35 U.S.C. § 103 (a).
Accordingly, we reverse or sustain the Examiner’s rejection of theses claims
based upon our decision regarding the rejection of the independent claims
upon which they depend.

CONCLUSION
Appellant’s arguments have persuaded us of error in the Examiner’s
rejection of independent claims 1, 19 and 40. Accordingly we reverse the
Examiner’s rejections of claims 1 through 4, 7 through 10, 19 through 23,
40, and 43 through 46 under 35 U.S.C. § 102 (e) and the Examiner’s
rejection of claims 5, 6, 41, and 42 under 35 U.S.C. § 103 (a)
However, Appellant’s arguments have not persuaded us of error in the
Examiner’s rejection of independent claim 35. Accordingly, we affirm the
Examiner’s rejection of claims 35, 36, 38 and 39 under 35 U.S.C. § 102 (e)
and the Examiner’s rejection of claim 37 under 35 U.S.C. § 103(a).

ORDER
The decision of the Examiner is affirmed-in-part.

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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2006).

AFFIRMED-IN-PART

KIS

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