Ex Parte Hadley

Patent Trial and Appeal Board

Sep 20, 2018

13455867 (P.T.A.B. Sep. 20, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO.
13/455,867
146568 7590
Entit Software LLC
500 Westover Drive
#12603
Sanford, NC 27330
FILING DATE FIRST NAMED INVENTOR
04/25/2012 Ted A. Hadley
09/24/2018
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
82962805 6927
EXAMINER
CROHN, MARK I
ART UNIT PAPER NUMBER
2857
NOTIFICATION DATE DELIVERY MODE
09/24/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
software.ip.mail@microfocus.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Exparte TED A. HADLEY
Appeal2018-000267
Application 13/455,867 1
Technology Center 2800
Before ADRIENE LEPIANE HANLON, GEORGE C. BEST, and BRIAN
D. RANGE, Administrative Patent Judges.
RANGE, Administrative Patent Judge.
DECISION ON APPEAL
SUMMARY
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner's
decision rejecting claims 1-5 and 16-22. We have jurisdiction. 35 U.S.C.
§ 6(b ).
We AFFIRM.
1 According to Appellant, the real party in interest is Hewlett Packard
Enterprise Development LP ("HPED"). Appeal Br. 3. Appellant states
"HPED ... is a wholly-owned affiliate of Hewlett Packard Enterprise" and
its general or managing partner is Enterprise DC Holdings LLC. Id.
Appeal 2018-000267
Application 13/455,867
STATEMENT OF THE CASE2
Appellant describes the invention as relating to a processor that
determines when measurements are outside of a predetermined range so that
a security function may be performed if such measurements are detected.
Spec. ,r 10. Claim 1, reproduced below with emphasis added to certain key
recitations, is illustrative of the claimed subject matter:
1. A microprocessor comprising:
a multiplexer having inputs connected to a plurality of
sensors and connected to an external port via a switch, wherein
each sensor of the plurality of sensors outputs a voltage
representative of a measured characteristic of the
microprocessor; and
an analog to digital converter (ADC) having an input
connected to an output of the multiplexer, wherein the
microprocessor is to determine whether a characteristic
measured by one of the plurality of sensors is within a
predetermined range based on signal values output from the
ADC and an offset signal received from an external system
via the external port.
Appeal Br. 14 (Claims App.).
REFERENCES
The Examiner relies upon the prior art below in rejecting the claims
on appeal:
Finley et al.
("Finley")
Balard et al.
("Balard")
us 5,450,082
US 6,396,426 B 1
Sep. 12, 1995
May 28, 2002
2 In this Decision, we refer to the Final Office Action dated November 3,
2016 ("Final Act."), the Appeal Brief filed March 23, 2017 ("Appeal Br."),
the Examiner's Answer dated August 8, 2017 ("Ans."), and the Reply Brief
filed October 10, 2017 ("Reply Br.").
2
Appeal 2018-000267
Application 13/455,867
Fayad et al.
("Fayad")
Koizumi et al. 3
("Koizumi")
US 2006/0059368 Al Mar. 16, 2006
W02011/08084I July 7, 2011
REJECTIONS
The Examiner maintains the following rejections on appeal:
Rejection 1. Claims 1-3, 5, 16, 17, and 19-22 under 35 U.S.C. § 103
as unpatentable over Balard. Final Act. 6.
Rejection 2. Claim 4 under 35 U.S.C. § 103 as unpatentable over
Balard in view of Fayad. Id. at 11.
Rejection 3. Claim 18 under 35 U.S.C. § 103 as unpatentable over
Balard in view of Finley and Koizumi. Id. at 12.
ANALYSIS
We review the appealed rejections for error based upon the issues
identified by Appellant and in light of the arguments and evidence produced
thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential),
cited with approval in In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011) ("[I]t
has long been the Board's practice to require an applicant to identify the
alleged error in the examiner's rejections."). After considering the evidence
presented in this Appeal and each of Appellant's arguments, we are not
persuaded that Appellant identifies reversible error. Thus, we affirm the
Examiner's rejections for the reasons expressed in the Final Office Action
and the Answer. We add the following primarily for emphasis.
3 The Examiner makes reference to Koizumi et al., US 2012/0326692 Al,
Dec. 27, 2012, as a translation. Final Act. 12. We do the same.
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Application 13/455,867
Appellant argues claims 1 and 20, the only independent claims on
appeal, as a group. Appeal Br. 8. The Appellant presents separate
arguments for claims 2, 4, 5, and 19. We limit our discussion to claims 1, 2,
4, 5, and 19. Consistent with the provisions of 37 C.F.R. § 4I.37(c)(l)(iv)
(2013), all remaining claims will stand or fall with claim 1.
The Examiner rejects claims 1, 2, 5, and 19 under 35 U.S.C. § 103 as
unpatentable over Balard. Final Act. 6 ( citing Balard). The Examiner finds
that Balard teaches a microprocessor comprising each recitation of claim 1.
Final Act. 6-8. In the Answer, the Examiner explains that the structure of
claim 1 is illustrated by Appellant's Figure 2. Ans. 3. The Examiner
explains that Balard Figure 2 illustrates corresponding structure having
similar arrangement of, for example, sensors, a multiplexer, an offset signal,
and an analog to digital converter. Ans. 4---6.
With respect claim 1, Appellant argues that Balard "is solely
concerned with detecting whether the input pin is shorted or open circuited."
Appeal Br. 7-8. Appellant therefore maintains that Balard "fails to disclose
or render obvious a microprocessor ( or any other circuit) to determine
whether a characteristic measured by a sensor is within a predetermined
range." Id. at 8. The Examiner, however, persuasively explains how Balard
teaches that it determines whether a characteristic measured by one of the
plurality of sensors is within a predetermined range based on the inputs
recited by claim 1. Ans. 8-12. The preponderance of the evidence supports,
for example, the Examiner's finding that Balard teaches use of offset signals
in testing a sensor. See, e.g., id. at 9-10 (citing Balard 6:1-9). The
Examiner finds, for example, that Balard "is testing the sensors through
voltage ranges defined by the composite of the sensor voltages and the
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Application 13/455,867
applied offsets." Id. at 10 (citing Balard Figs. 6A---6C). The Examiner also
finds that Balard teaches its circuit may be incorporated into a
microprocessor. Id. at 10 ( citing Balard 8: 62---63 ("failure detection can be
incorporated onto a microprocessor")). Appellant does not persuasively
explain why the Examiner's findings in this regard are incorrect. We thus
sustain the Examiner's rejection of claim 1.
Claim 2 recites, "The microprocessor of claim 1, comprising a resistor
connected between the switch and the output of the multiplexer, wherein
responsive to the switch being closed, a voltage output from one of the
plurality of sensors selected by the multiplexer is readable across the resistor
from the external port." Appeal Br. 14 (Claims App.). The Examiner finds
that Balard resistor 106 ( depicted in Balard Figure 2) meets this recitation.
Final Act. 8. The Examiner also finds that VreLHi as depicted in Balard
Figure 2 is an external port that would enable the recited reading of a
voltage.
Appellant argue that resistor 106 "merely couples the reference
voltage to the input of the ADC 206." Appeal Br. 9. Appellant also argues
that Balard does not teach an external port as recited. Reply Br. 2-3. The
preponderance of the evidence does not support Appellant's arguments.
Rather, Balard Figure 2 indicates that resistor 106 is connected to the
multiplexer which, in tum, is connected to the sensors. Resistor 106 is also
connected to VreLHi which the Examiner identifies as an external port. Ans.
12-13. Appellant does not persuasively dispute the Examiner's finding that
"the resistor would be readable in Balard by connection from VreLhi ...
across the resistor to ground." Ans. 13. Appellant's argument does not
identify a structural difference between claim 2 and Balard. Because
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Application 13/455,867
Appellant does not persuasively identify reversible error, we sustain the
rejection of claim 2.
Claim 5 recites, "The microprocessor of claim 1, wherein a voltmeter
is to be connected to the external port if the switch is closed to read the
voltages generated by the plurality of sensors as each sensor of the plurality
of sensors is selected by the multiplexer." Appeal Br. 15 (Claims App.).
Claim 5 is an apparatus claim, but it merely recites an intended use of the
claimed microprocessor. Moreover, the recitation describes a future,
contingent intended use only when a certain scenario occurs (if the switch is
closed). "A patent applicant is free to recite features of an apparatus either
structurally or functionally. Yet, choosing to define an element
functionally, i.e., by what it does, carries with it a risk." In re Schreiber, 128
F.3d 1473, 1478 (Fed. Cir. 1997) (internal citation omitted). Functional
language is not given patentable weight if the prior art structure can
inherently perform the function. See id.
Appellant argues that it is unclear "why one of ordinary skill in the
art, in view of Balard's disclosure, would have derived a voltmeter that is
connected as set forth in claim 5." Appeal Br. 10. Claim 5 does not require
a voltmeter, however, it only requires (at most) a microprocessor to which a
voltmeter could be connected to obtain the recited reading. The Examiner
finds that Balard teaches such a microprocessor structure (Ans. 14), and
Appellant do not persuasively dispute the Examiner's position. We thus
sustain the rejection of claim 5.
Claim 19 recites, "The microprocessor of claim 1, wherein the
plurality of sensors are to be calibrated by closing the switch and reading the
voltages generated by the plurality of sensors via the external port by the
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Application 13/455,867
external system as the multiplexer selects each of the plurality of sensors and
as each sensor of the plurality of sensors is tested throughout its range."
Appeal Br. 15 (Claims App.). Claim 19, like claim 5, recites an intended
use. The Examiner finds that the Balard microprocessor would be capable
of being calibrated in the fashion recited by claim 19. Final Act. 19. The
Examiner's position is supported by the preponderance of the evidence. See,
e.g., Balard Fig. 2. Appellant does not persuasively dispute the Examiner's
finding. Appeal Br. 10-11. We thus sustain the rejection of claim 19.
Claim 4 recites, "The microprocessor of claim 1, comprising switch
control logic to prevent the switch from being closed responsive to the
microprocessor being in a secure state of the microprocessor in which the
microprocessor stores encrypted data." Appeal Br. 14 (Claims App.). The
Examiner rejects claim 4 under 35 U.S.C. § 103 as unpatentable over Balard
in view of Fayad. Final Act. 11. The Examiner finds that Balard teaches
both a switch and multiplexer having open/disable positions but "does not
expressly discuss the switch from being closed responsive to the
microprocessor being in a secure state of the microprocessor in which the
microprocessor stores encrypted data." Id. at 11-12. The Examiner finds,
however, that Fayad teaches architecture accessible through a secure flow
switch. Id. The Examiner determines that "[i]t would have been obvious to
one of ordinary skill in the art to utilize the switch control in
microprocessors storing encrypted data, as taught in Fayad, to control the
switch to the external port described by Balard, in order to secure the
microprocessor against attack (paragraph [0004])." Id. at 12.
Appellant argues that Fayad is a FPGA (field programmable gate
array) logic circuit rather than analog and therefore could not be combined
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with Balard without destroying the function of Balard's analog switch.
Appeal Br. 12. Appellant does not, however, present evidence regarding the
incompatibility of Fayad's teachings with Balard.
The Examiner determines that it would have been obvious to control
Balard's sequence with logic gates including FPGA logic gates. Ans. 16.
The Examiner states, "[t]he FPGA logic attributed to Fayad would have
been an obvious substitution for the logic gate control the [sic] switch taught
in Balard." Id. (finding that the analog switches in Balard offer the
equivalent of a secure state). Appellant argues that the Examiner does not
explain how the substitution would work (Reply Br. 3--4), but Appellant
does not persuasively dispute the Examiner's findings or persuasively argue
that Balard could not be modified to store encrypted data using Fayad's
FPGA logic gates. Because Appellant does not identify reversible error, we
sustain this rejection.
DECISION
For the above reasons, we affirm the Examiner's rejections of
claims 1-5 and 16-22.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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