Ex Parte Guthrie et alDownload PDFBoard of Patent Appeals and InterferencesMar 24, 201111056721 (B.P.A.I. Mar. 24, 2011) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/056,721 02/11/2005 Guy L. Guthrie AUS920041109US1 2000 50170 7590 03/24/2011 IBM CORP. (WIP) c/o WALDER INTELLECTUAL PROPERTY LAW, P.C. 17330 PRESTON ROAD SUITE 100B DALLAS, TX 75252 EXAMINER SAVLA, ARPAN P ART UNIT PAPER NUMBER 2185 MAIL DATE DELIVERY MODE 03/24/2011 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ Ex parte GUY L. GUTHRIE, WILLIAM J. STARKE, DEREK E. WILLIAMS, and PHILLIP G. WILLIAMS ____________ Appeal 2009-008114 Application 11/056,7211 Technology Center 2100 ____________ Before JOSEPH L. DIXON, LANCE LEONARD BARRY, and JEAN R. HOMERE, Administrative Patent Judges. HOMERE, Administrative Patent Judge. DECISION ON APPEAL2 1 Filed on February 11, 2005. The real party in interest is International Business Machine Corp. (App. Br. 1.) 2 The two-month time period for filing an appeal or commencing a civil action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing, as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE” (paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery mode) shown on the PTOL-90A cover letter attached to this decision. Appeal 2009-008114 Application 11/056,721 2 I. STATEMENT OF THE CASE Appellants appeal under 35 U.S.C. § 134(a) (2002) from the Examiner’s final rejection of claims 15 through 18. (App. Br. 2.) Claims 1 through 14 and 19 have been cancelled. (Id.) We have jurisdiction under 35 U.S.C. § 6(b) (2008). We affirm-in-part. Appellants’ Invention Appellants invented a method for “improving the bandwidth of a cache directory by slicing the cache directory into two smaller directories and replicating the snooping logic for each sliced cached directory.” (Spec. 1, ll. 5-8.) Illustrative Claim Independent claims 15, 16, and 17 further illustrate the invention as follows: 15. A method for improving the bandwidth of a cache directory comprising the steps of: receiving a first and a second address; reading a value in a bit in each of said first and said second address; determining which of a first and a second cache directory to search for said first and said second address based on said value read in said first and said second address; wherein said first cache directory is comprised of entries indicating data stored in a cache memory at addresses with a value of zero at said bit, wherein said second cache directory is comprised of entries indicating data stored in said cache memory at addresses with a value of a logical one at said bit; sending said first address to a first multiplexer by a first unit when said value read in both said first and said second address is zero and said second address is selected to be transmitted to a second unit on a bypass path, wherein said first unit is configured to shift a cycle Appeal 2009-008114 Application 11/056,721 3 speed to a lower speed, wherein said second unit is configured to shift said cycle speed to a higher speed. 16. A method for improving the bandwidth of a cache directory comprising the steps of: receiving a first and a second address; reading a value in a bit in each of said first and said second address; determining which of a first and a second cache directory to search for said first and said second address based on said value read in said first and said second address; wherein said first cache directory is comprised of entries indicating data stored in a cache memory at addresses with a value of zero at said bit, wherein said second cache directory is comprised of entries indicating data stored in said cache memory at addresses with a value of a logical one at said bit; sending said first address to a first multiplexer when said value read in said first address is zero and said value read in said second address is a logical value of one. 17. A method for improving the bandwidth of a cache directory comprising the steps of: receiving a first and a second address; reading a value in a bit in each of said first and said second address; determining which of a first and a second cache directory to search for said first and said second address based on said value read in said first and said second address; wherein said first cache directory is comprised of entries indicating data stored in a cache memory at addresses with a value of zero at said bit, wherein said second cache directory is comprised of entries indicating data stored in said cache memory at addresses with a value of a logical one at said bit; receiving a first request to read from or write to an address from a processor and one of said first and said second address; selecting one of said first request from said processor and said one of said first and said second address by a first arbitration unit; receiving a second request to read from or write to an address from said processor and one of said first and said second address; and Appeal 2009-008114 Application 11/056,721 4 selecting one of said second request from said processor and said one of said first and said second address by a second arbitration unit. Prior Art Relied Upon The Examiner relies on the following prior art as evidence of unpatentability: Navarro US 2004/0230745 A1 Nov. 18, 2004 Simcha Gochman et al., The Intel® Pentium® M Processor: Microarchitecture and Performance, INTEL® TECH. J., May 21, 2003 at 21 (hereinafter “Gochman”). Rejections on Appeal The Examiner rejects the claims on appeal as follows: Claims 16 through 18 stand rejected under 35 U.S.C. § 102(e) as being anticipated by Navarro. Claim 15 stands rejected under 35 U.S.C. § 103(a) as being unpatentable over the combination of Navarro and Gochman. Appellants’ Contentions 1. Appellants contend that Navarro’s disclosure of each interleave address register selecting one of the late select signals from both pipes by utilizing its value of bit 55 does not teach “sending said first address to a first multiplexer when said value read in said first address is zero and said value read in said second address is a logical value of one,” as recited in independent claim 16. (App. Br. 5.) Appellants also argue that Navarro discloses utilizing the logical queue to store requests and, therefore, does not teach the claimed “multiplexer.” (Id. at 5-7; Reply Br. 2.) Further, Appellants allege that an ordinarily skilled artisan would have understood that Navarro’s logical queue does not perform the function of a multiplexer Appeal 2009-008114 Application 11/056,721 5 (i.e., selects one of the received input based on a select input). (Reply Br. 2- 3.) 2. Appellants contend that Navarro’s disclosure of a priority unit cannot teach both “a first arbitration unit” and “a second arbitration unit,” as recited in independent claim 17. (App. Br. 8-10; Reply Br. 3-4.) 3. Appellants contend that when a request is being processed in a mismatching pipe, Navarro discloses comparing the translation lookaside buffer (hereinafter “TLB”) index with that of the other pipe. (App. Br. 13- 15.) If the TLB index is equal, Appellants argue that Navarro discloses comparing the TLB hit set identifications from both pipes at a decision node. (Id.) Therefore, Appellants allege that Navarro does not teach or fairly suggest “sending said first address to a first multiplexer by a first unit when said value read in both said first and said second address is zero and said second address is selected to be transmitted to a second unit on a bypass path,” as recited in independent claim 15. (Id.) Moreover, Appellants contend that Navarro’s D-cache unit and logical address queue do not teach or fairly suggest the claimed “first unit” and “first multiplexer,” respectively. (Reply Br. 4-5.) Examiner’s Findings and Conclusions 1. The Examiner finds that Navarro discloses sending addresses (112 & 113) from the I-unit to the logical address queue. (Ans. 9.) The Examiner also finds that Navarro discloses that when bit 55 in address (112) is 0, and bit 55 in address (113) is 1, only address (112) is sent to the logical address queue. (Id.) Therefore, the Examiner finds that Navarro teaches “sending said first address to a first multiplexer when said value read in said first address is zero and said value read in said second address is a logical Appeal 2009-008114 Application 11/056,721 6 value of one,” as recited in independent claim 16. (Id.) Further, the Examiner finds Navarro’s logical address queue performs the same function as a multiplexer because the logical address queue receives address requests (112 & 113) and outputs the requests at (115). (Id. at 9-10.) 2. The Examiner finds that Navarro’s priority unit teaches both the “first arbitration unit” and “second arbitration unit,” as recited in independent claim 17, because it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. (Id. at 11-12.) 3. The Examiner finds that Appellants erroneously assert that Navarro’s D-cache unit teaches the “first unit,” as recited in independent claim 15. (Id. at 14.) The Examiner also finds that Navarro’s disclosure of sending a selected request down the mismatch pipe amounts to transmitting a selected address down a bypass path. (Id.) II. ISSUES 1. Have Appellants shown that the Examiner erred in finding that Navarro anticipates independent claim 16? In particular, the issue turns on whether Navarro teaches “sending said first address to a first multiplexer when said value read in said first address is zero and said value read in said second address is a logical value of one,” as recited in independent claim 16. 2. Have Appellants shown that the Examiner erred in finding that Navarro anticipates independent claim 17? In particular, the issue turns on whether Navarro teaches the following claim limitations: Appeal 2009-008114 Application 11/056,721 7 (a) “selecting one of said first request from said processor and said one of said first and said second address by a first arbitration unit,” as recited independent claim 17; and (b) “selecting one of said second request from said processor and said one of said first and said second address by a second arbitration unit,” as recited in independent claim 17. 3. Have Appellants shown that the Examiner erred in concluding that the combination of Navarro and Gochman renders independent claim 15 unpatentable? In particular, the issue turns on whether the proffered combination teaches or fairly suggests “sending said first address to a first multiplexer by a first unit when said value read in both said first and said second address is zero and said second address is selected to be transmitted to a second unit on a bypass path,” as recited in independent claim 15. III. FINDINGS OF FACT The following Findings of Fact (hereinafter “FF”) are shown by a preponderance of the evidence. Navarro FF 1. Navarro’s figure 2 depicts a D-cache unit located within a processor. (2: ¶ [0022],[0024].) When an I-unit issues its requests (112, 113) to the D-cache unit, Navarro discloses utilizing a priority unit (116) to arbitrate the requests (112, 113) among themselves and with any previously issued requests that are stored in the logical queue (114). (Id. at ¶ [0025].) Navarro disclose that the priority unit (116) determines how the requests are distributed among the two processing pipes via pipe registers (117, 118), and Appeal 2009-008114 Application 11/056,721 8 among the four cache interleaves via the four cache request registers (119). (Id.) FF 2. Navarro discloses that each pipe has its own physical directory. (Id. at ¶ [0028].) Navarro discloses that the split between each directory is based on address bit 55, with bit 0 being the most significant bit in an address. (Id.) Navarro discloses that the “A” pipe contains directory information with lines of address bit 55 being 0, while the “B” pipe contains directory information with lines of address 55 being 1. (Id.) FF 3. Navarro’s figure 3 depicts an algorithm for allowing an “implied” fetch processing to occur. (3: ¶ [0032].) In particular, if the directory indexes are the same between both pipes at decision node (213), Navarro discloses that the requests in both pipelines are to the same absolute line address. (Id.) If the decisions at decision nodes (212b) and (213) are true, Navarro discloses that the fetch going down the mismatch pipe will select the late set select from the matching pipe and, subsequently, acquire the desired data (215). (Id.) IV. ANALYSIS 35 U.S.C. § 102(e) Rejection—Navarro Claim 16 Independent claim 16 recites, in relevant part, “sending said first address to a first multiplexer when said value read in said first address is zero and said value read in said second address is a logical value of one.” As detailed in the Findings of Fact section above, Navarro discloses a processor that contains an I-unit that issues data requests to a D-cache. (FF 1.) In particular, Navarro discloses that the I-unit issues two requests to a Appeal 2009-008114 Application 11/056,721 9 logical address queue before the requests are outputted to the priority unit for arbitration. (Id.) Further, Navarro discloses that the priority unit determines how the requests are distributed among two processing pipes. (Id.) Navarro discloses that requests are distributed to the “A” pipe when the lines of address bit 55 are 0, and the requests are distributed to the “B” pipe when the lines of address bit 55 are 1. (FF 2.) We find that Navarro’s disclosure teaches that the I-unit of the processor is capable of sending a first request to the logical address queue when a field of the first requested address has a value of 0, and sending a second request to the logical address queue when a field of the second requested address has a value of 1. Moreover, we find that Navarro’s logical address queue amounts to the claimed “first multiplexer.” That is, we find that Navarro’s logical address queue performs functions similar to the claimed “first multiplexer” because it is configured to receive multiple read or write requests, select one request, and output the selected request. (See Spec. 13, ll. 19-23; see also id. at 16, ll. 4-10.) Thus, we find that Navarro teaches the disputed limitation. It follows that Appellants have not shown that the Examiner erred in finding that Navarro anticipates independent claim 16. Claim 17 Independent claim 17 recites, in relevant part: 1) selecting one of said first request from said processor and said one of said first and said second address by a first arbitration unit; and 2) selecting one of said second request from said processor and said one of said first and said second address by a second arbitration unit. Based on our analysis above, we find that Navarro’s disclosure, at best, teaches a single priority unit that is capable of selecting and diverting Appeal 2009-008114 Application 11/056,721 10 requests based on whether a field within each requested address has a value of 0 or 1. (FFs 1 & 2.) However, we agree with Appellants that Navarro fails to teach a first arbitration unit that selects the first request and one of the first or second address, and a second arbitration unit that selects the second request and one of the first or second address. (App. Br. 8-10; Reply Br. 3-4.) Therefore, Navarro’s disclosure fails to teach or suggest two separate and distinct priority units that are both capable of selecting and diverting requests. Moreover, we note that while an ordinarily skilled artisan would have appreciated that constructing Navarro’s priority unit into various elements involves only routine skill in the art (e.g., splitting Navarro’s priority unit into two priority units) (Ans. 11-12), such a finding is insufficient for anticipation. Therefore, we find that the Examiner improperly relied upon Navarro’s disclosure to teach the disputed limitations. Since Appellants have shown at least one error in the rejection of independent claim 17, we need not reach the merits of Appellants’ other arguments. It follows that Appellants have shown that the Examiner erred in finding that Navarro anticipates independent claim 17. Claim 18 Since dependent claim 18 also incorporates the limitations discussed above, we find that Appellants have also shown error in the Examiner’s rejection of this claim for the reasons set forth in our discussion of independent claim 17. Appeal 2009-008114 Application 11/056,721 11 35 U.S.C. § 103(a) Rejection—Combination of Navarro and Gochman Claim 15 Independent claim 15 recites, in relevant part, “sending said first address to a first multiplexer by a first unit when said value read in both said first and said second address is zero and said second address is selected to be transmitted to a second unit on a bypass path.” As detailed in the Findings of Fact section above, Navarro discloses that if the directory indexes are the same between pipes “A” and “B,” the requests in both pipelines are to the same absolute line address. (FF 3.) At best, we find that Navarro’s disclosure of requests having the same absolute line address teaches or fairly suggests a first and second request where a field within each requested address has a value of 0. However, we find that Navarro falls short of teaching or fairly suggesting a first frequency matcher sending a first address to a first multiplexer when the value read in both the first and second address is 0, let alone transmitting the second address to a second frequency matcher on a bypass path. Although Navarro teaches a first and second request where a field within each requested address has a value of 0, the reference is silent with regards to sending or transmitting the first and second requests down different paths. Therefore, since Navarro does not teach or fairly suggest a first frequency matcher sending the first address to the logical address queue, and transmitting the second address to a second frequency matcher down a bypass path, we find that the Examiner improperly relied upon Navarro’s disclosure to teach or fairly suggest the disputed limitation. Further, we note that Gochman does not remedy the noted deficiencies in the Examiner’s rejection. Appeal 2009-008114 Application 11/056,721 12 Since Appellants have shown at least one error in the rejection of independent claim 15, we need not reach the merits of Appellants’ other arguments. It follows that Appellants have shown that the Examiner erred in concluding that the combination of Navarro and Gochman renders independent claim 15 unpatentable. V. CONCLUSIONS OF LAW 1. Appellants have not shown that the Examiner erred in rejecting claim 16 as being anticipated under 35 U.S.C. § 102(e). 2. Appellants have shown that the Examiner erred in rejecting claims 17 and 18 as being anticipated under 35 U.S.C. § 102(e). 3. Appellants have shown that the Examiner erred in rejecting claim 15 as being unpatentable under 35 U.S.C. § 103(a). VI. DECISION 1. We affirm the Examiner’s decision to reject claim 16 as being anticipated under 35 U.S.C. § 102(e). 2. We reverse the Examiner’s decision to reject claims 17 and 18 as being anticipated under 35 U.S.C. § 102(e). 3. We reverse the Examiner’s decision to reject claim 15 as being unpatentable under 35 U.S.C. § 103(a). No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). AFFIRMED-IN-PART Vsh Appeal 2009-008114 Application 11/056,721 13 IBM CORP. (WIP) c/o WALDER INTELLECTUAL PROPERTY LAW, P.C. 17330 PRESTON ROAD SUITE 100B DALLAS, TX 75252 Copy with citationCopy as parenthetical citation